Holtek HT32F12345 User Manual page 276

32-Bit Arm ® Cortex ® -M3 MCU
HT32F12345
Bits Field
[4] CH0OCF
[3] CH3CCIF
[2] CH2CCIF
[1] CH1CCIF
[0] CH0CCIF
Rev. 1.10
Descriptions
Channel 0 Over-Capture Flag
0: No over-capture event is detected
1: Capture event occurs again when the CH0CCIFbit is already set and it is not
yet cleared by software
This flag is set by hardware and cleared by software writing a '0'.
Channel 3 Capture / Compare Interrupt Flag
- Channel 3 is configured as an output:
0: No match event occurs
1: The contents of the counter CNTR have matched the contents of the CH3CCR
register
This flag is set by hardware when the counter value matches the CH3CCR value
except in the center-aligned mode. It is cleared by software.
- Channel 3 is configured as an input:
0: No input capture occurs
1: Input capture occurs
This bit is set by hardware on a capture event. It is cleared by software or by reading
the CH3CCR register.
Channel 2 Capture / Compare Interrupt Flag
- Channel 2 is configured as an output:
0: No match event occurs
1: The contents of the counter CNTR have matched the contents of the CH2CCR
register
This flag is set by hardware when the counter value matches the CH2CCR value
except in the center-aligned mode. It is cleared by software.
- Channel 2 is configured as an input:
0: No input capture occurs
1: Input capture occurs
This bit is set by hardware on a capture event. It is cleared by software or by reading
the CH2CCR register.
Channel 1 Capture / Compare Interrupt Flag
Channel 1 is configured as an output:
0: No match event occurs
1: The contents of the counter CNTR have matched the contents of the CH1CCR
register
This flag is set by hardware when the counter value matches the CH1CCR value
except in the center-aligned mode. It is cleared by software.
- Channel 1 is configured as an input:
0: No input capture occurs
1: Input capture occurs
This bit is set by hardware on a capture event. It is cleared by software or by reading
the CH1CCR register.
Channel 0 Capture / Compare Interrupt Flag
- Channel 0 is configured as an output:
0: No match event occurs
1: The contents of the counter CNTR have matched the content of the CH0CCR
register
This flag is set by hardware when the counter value matches the CH0CCR value
except in the center-aligned mode. It is cleared by software.
- Channel 0 is configured as an input:
0: No input capture occurs
1: Input capture occurs
This bit is set by hardware on a capture event. It is cleared by software or by reading
the CH0CCR register.
276 of 590 November 28, 2018