Holtek HT32F12345 User Manual page 427

32-Bit Arm ® Cortex ® -M3 MCU
HT32F12345
Bits Field
[8] BUSY
[7] TO
[6] SA
[5] MF
[4] RO
[3] WC
[2] RXBNE
[1] TXE
[0] TXBE
Rev. 1.10
Descriptions
SPI Busy flag
0: SPI not busy
1: SPI busy
In the master mode, this flag is reset when the TX buffer and TX shift register are
both empty and is set when the TX buffer or the TX shift register are not empty.
In the slave mode, this flag is set when SEL changes to an active level and is reset
when SEL changes to an inactive level.
Time out flag
0: No RX FIFO time out
1: RX FIFO time out has occurred
Write 1 to clear it.
Once the time out counter value is equal to the TOC field setting in the SPIFTOCR
register, the time out flag will be set and an interrupt will be generated if the TOIEN
bit in the SPIIER register is enabled. This bit is cleared by writing 1.
Note: This Time Out flag function is only available in the SPI FIFO mode.
Slave Abort flag
0: No slave abort
1: Slave abort has occurred
This bit is set by hardware and cleared by writing 1.
Mode Fault flag
0: No mode fault
1: Mode fault has occurred
This bit is set by hardware and cleared by writing 1.
Read Overrun flag
0: No read overrun
1: Read overrun has occurred.
This bit is set by hardware and cleared by writing 1.
Write Collision flag
0: No write collision
1: Write collision has occurred
This bit is set by hardware and cleared by writing 1.
Receive Buffer Not Empty flag
0: RX buffer empty
1: RX buffer not empty
This bit indicates the RX buffer status in the non-FIFO mode. It is also used to
indicate if the RX FIFO trigger level has been reached in the FIFO mode. This bit will
be cleared when the SPI RX buffer is empty in the non-FIFO mode or if the number
of data contained in RX FIFO is less than the trigger level which is specified by the
RXFTLS field in the SPIFCR register in the SPI FIFO mode.
Transmission Register Empty flag
0: TX buffer or TX shift register is not empty
1: TX buffer and TX shift register both are empty
Transmit Buffer Empty flag
0: TX buffer not empty
1: TX buffer empty
In the FIFO mode, this bit indicates that the number of data contained in TX FIFO is
equal to or less than the trigger level specified by the TXFTLS field in the SPIFCR
register.
427 of 590 November 28, 2018