Flash Memory Architecture; Wait State Setting; Table 4. Flash Memory And Option Byte; Table 5. Relationship Between Wait State Cycle And Hclk - Holtek HT32F12345 User Manual

32-Bit Arm ® Cortex ® -M3 MCU
HT32F12345

Flash Memory Architecture

The Flash memory consists of 63 KB main Flash with 1 KB per page and an 4 KB Information
Block for the Boot Loader. The main Flash memory contains a total of 64 pages which can be
erased individually. The following table shows the base address, size and protection setting bit of
each page.

Table 4. Flash Memory and Option Byte

Block Name
Page 0
Page 1
Page 2
Page 3
. .
Main Flash
. .
. .
.
Block
Page 60
Page 61
Page 62
Page 63
(Option Byte)
Information
Boot Loader 0x1F00_0000 ~ 0x1F00_0FFF
Block
Notes: 1. Information Block stores boot loader, this block cannot be programmed or erased by user.
2. Option Byte is always located at last page of main Flash block.

Wait State Setting

When the CPU clock, HCLK, is greater than the access speed of the Flash memory, the wait state
cycles must be inserted during the CPU fetch instructions or load data from Flash memory. The
wait state can be changed by setting the WAIT [2:0] bits of the Flash Cache and Pre-fetch Control
Register, CFCR. In order to match the wait state requirement, the following two rules shall be
considered.
▄
HCLK clock is changed from lower to higher:
Change the wait state setting first and then switch the HCLK clock.
▄
HCLK clock is changed from higher to lower:
Switch the HCLK clock first and then change the wait state setting.
The following table shows the relationship between the wait state cycle and HCLK. The default
wait state is 0 since the High Speed Internal oscillator HSI which operates at a frequency of 8 MHz
is selected as the HCLK clock source after reset.

Table 5. Relationship between Wait State Cycle and HCLK

Rev. 1.10
Address
0x0000_0000 ~ 0x0000_03FF
0x0000_0400 ~ 0x0000_07FF
0x0000_0800 ~ 0x0000_0BFF
0x0000_0C00 ~ 0x0000_0FFF
. .
. .
. .
.
0x0000_F000 ~ 0x0000_F3FF
0x0000_F400 ~ 0x0000_F7FF
0x0000_F800 ~ 0x0000_FBFF
Physical: 0x0000_FC00 ~ 0x0000_FFFF
Alias: 0x1FF0_0000 ~ 0x1FF0_03FF
Wait State Cycle
0
1
2
3
44 of 590
Page Protection Bit
OB_PP [0]
OB_PP [1]
OB_PP [2]
OB_PP [3]
. .
. .
. .
.
OB_PP [60]
OB_PP [61]
OB_PP [62]
OB_CP [1]
NA
HCLK
0 MHz < HCLK ≤ 24 MHz
24 MHz < HCLK ≤ 48 MHz
48 MHz < HCLK ≤ 72 MHz
72 MHz < HCLK ≤ 96 MHz
November 28, 2018
Size
1 KB
1 KB
1 KB
1 KB
. .
. .
. .
.
1 KB
1 KB
1 KB
1 KB
4 KB