Holtek HT32F12345 User Manual page 24

32-Bit Arm ® Cortex ® -M3 MCU
HT32F12345
Figure 121. CH1XOR Input as Hall Sensor Interface ........................................................................... 323
Figure 122. MCTM PDMA Mapping Diagram ....................................................................................... 325
Figure 123. RTC Block Diagram ........................................................................................................... 365
Figure 124. Watchdog Timer Block Diagram ....................................................................................... 375
Figure 125. Watchdog Timer Behavior ................................................................................................. 377
Figure 126. I 2 C Module Block Diagram ................................................................................................. 384
Figure 127. START and STOP Condition ............................................................................................. 386
Figure 128. Data Validity ....................................................................................................................... 386
Figure 129. 7-bit Addressing Mode ....................................................................................................... 387
Figure 130. 10-bit Addressing Write Transmit Mode ............................................................................ 387
Figure 131. 10-bits Addressing Read Receive Mode .......................................................................... 388
Figure 132. I 2 C Bus Acknowledge ........................................................................................................ 388
Figure 133. Clock Synchronization during Arbitration ........................................................................... 389
Figure 134. Two Master Arbitration Procedure ..................................................................................... 389
Figure 135. Master Transmitter Timing Diagram .................................................................................. 391
Figure 136. Master Receiver Timing Diagram ...................................................................................... 393
Figure 137. Slave Transmitter Timing Diagram .................................................................................... 394
Figure 138. Slave Receiver Timing Diagram ........................................................................................ 395
Figure 139. SCL Timing Diagram .......................................................................................................... 406
Figure 140. SPI Block Diagram .............................................................................................................411
Figure 141. SPI Single Byte Transfer Timing Diagram - CPOL = 0, CPHA = 0 .................................... 413
Figure 142. SPI Continuous Data Transfer Timing Diagram - CPOL = 0, CPHA = 0 ........................... 414
Figure 143. SPI Single Byte Transfer Timing Diagram - CPOL = 0, CPHA = 1 .................................... 414
Figure 144. SPI Continuous Transfer Timing Diagram - CPOL = 0, CPHA = 1 .................................... 415
Figure 145. SPI Single Byte Transfer Timing Diagram - CPOL = 1, CPHA = 0 .................................... 415
Figure 146. SPI Continuous Transfer Timing Diagram - CPOL = 1, CPHA = 0 .................................... 416
Figure 147. SPI Single Byte Transfer Timing Diagram - CPOL = 1, CPHA = 1 .................................... 416
Figure 148. SPI Continuous Transfer Timing Diagram - CPOL = 1, CPHA = 1 .................................... 417
Figure 149. SPI Multi-Master Slave Environment ................................................................................. 418
Figure 150. USART Block Diagram ...................................................................................................... 431
Figure 151. USART Serial Data Format ............................................................................................... 433
Figure 152. USART Clock CK_USART and Data Frame Timing .......................................................... 433
Figure 153. Hardware Flow Control between 2 USARTs ...................................................................... 434
Figure 154. USART RTS Flow Control ................................................................................................. 435
Figure 155. USART CTS Flow Control ................................................................................................. 435
Figure 156. IrDA Modulation and Demodulation ................................................................................... 436
Figure 157. USART I/O and IrDA Block Diagram ................................................................................. 437
Figure 158. RS485 Interface and Waveform ........................................................................................ 438
Figure 159. USART Synchronous Transmission Example ................................................................... 439
Figure 160. 8-bit Format USART Synchronous Waveform ................................................................... 440
Figure 161. UART Block Diagram ......................................................................................................... 455
Rev. 1.10 24 of 590 November 28, 2018