Register Descriptions; Timer Counter Configuration Register - Cntcfr - Holtek HT32F12345 User Manual

32-Bit Arm ® Cortex ® -M3 MCU
HT32F12345

Register Descriptions

Timer Counter Configuration Register – CNTCFR
This register specifies the MCTM counter configuration.
Offset: 0x000
Reset value: 0x0000_0000
31
Type/Reset
23
Type/Reset
15
Type/Reset
7
Type/Reset
Bits Field
[24] DIR
[17:16] CMSEL
[9:8] CKDIV
Rev. 1.10
30 29 28
Reserved
22 21 20
Reserved
14 13 12
Reserved
6 5
Reserved
Descriptions
Counting Direction
0: Count-up
1: Count-down
Note: This bit is read only when the Timer is configured to be in the Center-aligned
counting mode or when used as a Quadrature decoder
Counter Mode Selection
00: Edge-aligned counting mode. Normal up-counting and down-counting
available for this mode. Counting direction is defined by the DIR bit.
01: Center-aligned counting mode 1. The counter counts up and down
alternatively. The compare match interrupt flag is set during the count-down
period.
10: Center-aligned counting mode 2. The counter counts up and down
alternatively. The compare match interrupt flag is set during the count-up
period.
11: Center-aligned counting mode 3. The counter counts up and down
alternatively. The compare match interrupt flag is set during the count-up and
count-down period.
Clock Division
These two bits define the frequency ratio between the timer clock (f
dead-time clock (f ). The dead-time clock is also used as the digital filter sampling
DTS
clock
00: f = f
DTS CLKIN
01: f = f / 2
DTS CLKIN
10: f = f / 4
DTS CLKIN
11: Reserved
327 of 590
27 26
19 18
11 10
4 3 2
25 24
DIR
RW 0
17 16
CMSEL
RW 0 RW 0
9 8
CKDIV
RW 0 RW 0
1 0
UGDIS UEV1DIS
RW 0 RW 0
) and the
CLKIN
November 28, 2018