Irda; Figure 156. Irda Modulation And Demodulation - Holtek HT32F12345 User Manual

32-Bit Arm ® Cortex ® -M3 MCU
HT32F12345

IrDA

The USART IrDA mode is provided half-duplex point-to-point wireless communication.
The USART module includes an integrated modulator and demodulator which allow a wireless
communication using infrared transceivers. The transmitter specifies a logic data '0' as a 'high'
pulse and a logic data '1' as a 'low' level while the receiver specifies a logic data '0' as a 'low' pulse
and a logic data '1' as 'high' level in the IrDA mode.
START
TX_Data 1 0
IrDA TX
Modulation
Signal
bit width
IrDA RX
Demodulation
Signal
1
RX_Data

Figure 156. IrDA Modulation and Demodulation

The IrDA mode provides two operation modes, one is the normal mode, and the other is the low-
power mode.
IrDA Normal Mode
For the IrDA normal mode, the width of each transmitted pulse generated by the transmitter
modulator is specified as 3/16 of the baud rate clock period. The receiver pulse width for the IrDA
receiver demodulator is based on the IrDA receive debounce filter which is implement using an
8-bit down-counting counter. The debounce filter counter value is specified by the IrDAPSC field
in the IrDACR register. When a falling edge is detected on the receiver pin, the debounce filter
counter starts to count down, driven by the CK_USART clock. If a rising edge is detected on the
receiver pin, the counter stops counting and is reloaded with the IrDAPSC value. When a low
pulse falling edge on the receiver pin is detected and then before the debounce filter has counted
down to zero, a rising edge is also detected, then this low pulse will be considered as glitch noise
and will be discarded. If a low pulse falling edge appears on the receiver pin but no rising edge
is detected before the debounce counter reaches 0, then the input is regarded as a valid data "0"
for this bit duration. The IrDAPSC value must be set to be greater than or equal to 0x01, then the
Rev. 1.10
1 0 1
START
0 1 0 1
436 of 590
Data Frame
0 1 1 1
3/16 bit width
Data Frame
0 1 1
STOP
0
STOP
1 0
November 28, 2018