Ebi Parity Register N - Ebipr, N = 0 ~ 3 - Holtek HT32F12345 User Manual

32-Bit Arm ® Cortex ® -M3 MCU
HT32F12345
EBI Parity Register n – EBIPR, n = 0 ~ 3
This register specifies the polarity of the EBI control signal for bank n. (n = 0 ~ 3)
Offset: 0x01C (n = 0), 0x2C (n = 1), 0x3C (n = 2), 0x4C (n = 3)
Reset value: 0x0000_0000
31
Type/Reset
23
Type/Reset
15
Type/Reset
7
Reserved
Type/Reset
Bits Field
[5] BLPOL
[4] ARDYPOL
[3] ALEPOL
[2] WEPOL
[1] OEPOL
[0] CSPOL
Rev. 1.10
30 29 28
22 21 20
14 13 12
6 5 4
BLPOL ARDYPOL
RW 0 RW
Descriptions
Byte Lane Polarity
0: EBI_BL is active low
1: EBI_BL is active high
Set the polarity of the EBI_BL line
Asynchronous Ready Polarity
0: EBI_ARDY is active low
1: EBI_ARDY is active high
Set the polarity of the EBI_ARDY line
Address Latch Polarity
0: EBI_ALE is active low
1: EBI_ALE is active high
Set the polarity of the EBI_ALE line
Write Enable Polarity
0: EBI_WE is active low
1: EBI_WE is active high
Set the polarity of the EBI_WE line.
Output Enable Polarity
0: EBI_OE is active low
1: EBI_OE is active high
Set the polarity of the EBI_OE line.
Chip Selection Polarity
0: EBI_CS is active low
1: EBI_CS is active high
Set the polarity of the EBI_CSn line.
536 of 590
27 26
Reserved
19 18
Reserved
11 10
Reserved
3 2
ALEPOL WEPOL
0 RW 0 RW 0 RW
25 24
17 16
9 8
1 0
OEPOL CSPOL
0 RW 0
November 28, 2018