32-Bit Arm
®
Cortex
®
-M3 MCU
HT32F12345
26
Inter-IC Sound (I
Introduction
The I
2
S is a synchronous communication interface that can be used as a master or slave to
exchange data with other audio peripherals, such as ADCs or DACs. The I
data formats. In addition to the stereo I
are mono PCM modes with 8/16/24/32-bit sample size. When the I
then when using the fractional divider, it can provide an accurate sampling frequency output and
support the rate control function and fine-tuning of the output frequency to avoid system problems
caused by the cumulative frequency error between different devices.
APB
Interface
&
Control
Registers
PDMA Req
PDMA Ack
Figure 188. I
2
S Block Diagram
Features
▄
Master or slave mode
▄
Mono and stereo
▄
I
2
S-justified, Left-justified and Right-justified mode
▄
8/16/24/32-bit sample size with 32-bit channel extended
▄
8 × 32-bit TX FIFO and RX FIFO with PDMA supported
▄
8-bit Fractional Clock Divider with rate control
Rev. 1.10
2
S-justified, Left-justified and Right-justified modes, there
2
2
I
S Clock Generator
TX FIFO
TX Shift Register
RX FIFO
RX Shift Register
Mster/Slave
539 of 590
S)
2
S operates in the master mode,
2
S supports a variety of
I2SMCLK
I2SWS
I2SDO
I2SBCLK
I2SDI
November 28, 2018
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