I 2 S Clock Rate Generator; Table 69. Recommend Fs List @ 8 Mhz Pclk; Figure 190. I S Clock Generator Diagram - Holtek HT32F12345 User Manual

32-Bit Arm ® Cortex ® -M3 MCU
HT32F12345
I 2 S Clock Rate Generator
The main (I2S_MCLK) and bit clock (I2S_BCLK) rates for the I
in the I2SCDR register. The required I
rate desired, the format (stereo / mono) used and the data size. The main clock rate (I2S_MCLK)
is generated using a fractional rate divider which is a divided down PCLK frequency of the I
Values of the numerator (X) and the denominator (Y) must be chosen to produce a frequency twice
that of the main clock (I2S_MCLK). The output frequency of the divider is divided by 2 in order to
get the duty cycle of the output clock more even. The I
Figure 190. The equation for the fractional rate divider is:
I2S_MCLK = (1/2) × PCLK × (X/Y), and X/Y ≤ 1, X = 1 ~ 255, Y = 1 ~ 255
Because the fractional rate divider is a fully digital implementation function, the divider output
clock transitions are synchronous with the input source clock. Therefore, the fractional rate divider
will generate some jitter with some divider settings. Users should make note of this phenomenon
when choosing the X and Y setup values. It is possible to avoid jitter entirely by choosing fractions
such that X divides evenly into Y, for example, 2/4, 2/6, 3/9, etc.
The tables below show the recommended setup values to reduce clock jitter for different source
clocks and sample rates.
PCLK
Figure 190. I 2 S Clock Generator Diagram

Table 69. Recommend FS List @ 8 MHz PCLK

512 F
Fs (Hz) X
8,000 —
11,025 —
12,000 —
16,000 —
22,050 —
24,000 —
32,000 —
44,100 —
48,000 —
96,000 —
192,000 —
Rev. 1.10
2 S bit clock rate setting depends on the desired audio sample
I2S_BCLK = I2S_MCLK / (N+1), N = 0 ~ 255
2
I S Clock Generator
X Y
8-bit Fractional
Rate Divider
2
& Fine-Tuning
Controller
384 F 256 F
S S
Y X Y X
— 96 125 64
— — — 170
— — — 96
— — — —
— — — —
— — — —
— — — —
— — — —
— — — —
— — — —
— — — —
541 of 590
2 S are determined by the values
2 S clock generator block diagram is shown in
I2S_MCLK
(N + 1) I2S_BCLK
2
I S Control
I2S_WS
Logic
192 F 128 F
S S
Y X Y X
125 48 125 32
241 118 223 90
125 72 125 48
— 96 125 64
— — — 170
— — — 96
— — — —
— — — —
— — — —
— — — —
— — — —
S.
2
64 F
S S
Y X Y
125 16 125
255 42 238
125 24 125
125 32 125
241 90 255
125 48 125
— 64 125
— 170 241
— 96 125
— — —
— — —
November 28, 2018