32-Bit Arm
®
Cortex
®
-M3 MCU
HT32F12345
PLL Control Register – PLLCR
This register specifies the PLL Bypass mode.
Offset:
0x01C
Reset value: 0x0000_0000
31
PLLBPS
Type/Reset
RW
0
23
Type/Reset
15
Type/Reset
7
Type/Reset
Bits
Field
[31]
PLLBPS
Rev. 1.10
30
29
28
22
21
20
14
13
12
6
5
4
Descriptions
PLL Bypass Mode Enable
0: Disable PLL Bypass mode
1: Enable PLL Bypass mode which acts FOUT = FIN
100 of 590
27
26
Reserved
19
18
Reserved
11
10
Reserved
3
2
Reserved
25
24
17
16
9
8
1
0
November 28, 2018
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