Ebi Read Timing Register N - Ebirtrn, N = 0 ~ 3 - Holtek HT32F12345 User Manual

32-Bit Arm ® Cortex ® -M3 MCU
HT32F12345
EBI Read Timing Register n – EBIRTRn, n = 0 ~ 3
This register specifies the read timing setting for bank n. (n = 0 ~ 3)
Offset: 0x014 (n = 0), 0x24 (n = 1), 0x34 (n = 2), 0x44 (n = 3)
Reset value: 0x000F_3F0F
31
Type/Reset
23
Type/Reset
15
Reserved
Type/Reset
7
Type/Reset
Bits Field
[24] PGEN
[19:16] RDHOLD
[13:8] RDSTRB
[3:0] RDSETUP
Rev. 1.10
30 29 28
Reserved
22 21 20
Reserved
14 13 12
RW 1 RW
6 5 4
Reserved
Descriptions
Page Enable
0: Page read disable
1: Page read enable
This bit is used to enable the page read mode for the corresponding bank.
Read Hold Time
Sets the number of cycles that the EBI_CSn is held active for after EBI_OE is de-
asserted. This interval is used for bus turnaround.
Read Strobe Time
Sets the number of cycles that the EBI_OE is held active for. After the specified
number of cycles, the data is read. If set to 0, one cycle is inserted by the hardware.
The cycle unit is based on an HCLK clock period.
Read Setup Time
Sets the number of cycles for the address setup before EBI_OE is asserted. The
cycle unit is basic on an HCLK clock period.
534 of 590
27 26
19 18
RW 1 RW 1 RW
11 10
RDSTRB
1 RW 1 RW 1 RW
3 2
RDSETUP
RW 1 RW 1 RW
25 24
PGEN
RW 0
17 16
RDHOLD
1 RW 1
9 8
1 RW 1
1 0
1 RW 1
November 28, 2018