Holtek HT32F12345 User Manual page 22

32-Bit Arm ® Cortex ® -M3 MCU
HT32F12345
Figure 40. Down-counting Example ...................................................................................................... 226
Figure 41. Center-aligned Counting Example ....................................................................................... 227
Figure 42. GPTM Clock Selection Source ............................................................................................ 228
Figure 43. Trigger Control Block ........................................................................................................... 229
Figure 44. Slave Controller Diagram .................................................................................................... 230
Figure 45. GPTM in Restart Mode ........................................................................................................ 230
Figure 46. GPTM in Pause Mode ......................................................................................................... 231
Figure 47. GPTM in Trigger Mode ........................................................................................................ 231
Figure 48. Master GPTMn and Slave GPTMm/MCTMm Connection ................................................... 232
Figure 49. MTO Selection ..................................................................................................................... 232
Figure 50. Capture / Compare Block Diagram ...................................................................................... 233
Figure 51. Input Capture Mode ............................................................................................................. 233
Figure 52. PWM Pulse Width Measurement Example .......................................................................... 234
Figure 53. Channel 0 and Channel 1 Input Stage ................................................................................ 235
Figure 54. Channel 2 and Channel 3 Input Stage ............................................................................... 236
Figure 55. Output Stage Block Diagram ............................................................................................... 236
Figure 56. Toggle Mode Channel Output Reference Signal (CHxPRE = 0) ......................................... 237
Figure 57. Toggle Mode Channel Output Reference Signal (CHxPRE = 1) ......................................... 238
Figure 58. PWM Mode Channel Output Reference Signal and Counter in Up-counting Mode ........... 238
Figure 59. PWM Mode Channel Output Reference Signal and Counter in Down-counting Mode ....... 239
Figure 60. PWM Mode Channel Output Reference Signal and Counter in Centre-align Mode ............ 239
Figure 61. Update Event Setting Diagram ............................................................................................ 240
Figure 62. Input Stage and Quadrature Decoder Block Diagram ........................................................ 241
Figure 63. Both TI0 and TI1 Quadrature Decoder Counting ................................................................ 242
Figure 64. GTn_ETI Pin Digital Filter Diagram with N = 2 .................................................................... 242
Figure 65. Clearing CHOxREF by ETIF ................................................................................................ 243
Figure 66. Single Pulse Mode ............................................................................................................... 244
Figure 67. Immediate Active Mode Minimum Delay ............................................................................. 245
Figure 68. Asymmetric PWM Mode in Center-aligned Counting Mode ................................................ 246
Figure 69. Pausing GPTM1 Using the GPTM0 CH0OREF Signal ....................................................... 247
Figure 70. Triggering GPTM1 with GPTM0 Update Event .................................................................... 247
Figure 71. Trigger GPTM0 and GPTM1 with the GPTM0 CH0 Input ................................................... 248
Figure 72. GPTM PDMA Mapping Diagram .......................................................................................... 249
Figure 73. BFTM Block Diagram .......................................................................................................... 284
Figure 74. BFTM - Repetitive Mode ..................................................................................................... 285
Figure 75. BFTM - One Shot Mode ...................................................................................................... 286
Figure 76. BFTM - One Shot Mode Counter Updating ....................................................................... 286
Figure 77. MCTM Block Diagram ......................................................................................................... 291
Figure 78. Up-counting Example .......................................................................................................... 293
Figure 79. Down-counting Example ...................................................................................................... 294
Figure 80. Center-aligned Counting Example ....................................................................................... 295
Rev. 1.10 22 of 590 November 28, 2018