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Holtek HT45F8544 Manual

Bms flash mcu
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BMS Flash MCU
HT45F8544
Revision: V1.20
Date: January 31, 2024

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Summary of Contents for Holtek HT45F8544

  • Page 1 BMS Flash MCU HT45F8544 Revision: V1.20 Date: January 31, 2024...
  • Page 2 HT45F8544 BMS Flash MCU Table of Contents Features ......................... 7 CPU Features ..........................7 Peripheral Features ........................7 General Description ....................8 Block Diagram ....................... 9 Pin Assignment ..................... 9 Pin Description ....................10 Interconnection Signal Description ....................12 Absolute Maximum Ratings ................13 Recommended Operating Ratings ..............
  • Page 3 HT45F8544 BMS Flash MCU Look-up Table ..........................28 Table Program Example ......................29 In Circuit Programming – ICP .....................30 On-Chip Debug Support – OCDS ....................30 In Application Programming – IAP ....................31 Data Memory ....................... 47 Structure ............................47 Data Memory Addressing ......................48 General Purpose Data Memory ....................48 Special Purpose Data Memory ....................48...
  • Page 4 HT45F8544 BMS Flash MCU Reset and Initialisation ..................75 Reset Functions ..........................75 Reset Initial Conditions ......................80 Input/Output Ports ....................83 Pull-high Resistors ........................83 Port A Wake-up ...........................84 I/O Port Control Registers ......................85 I/O Port Source Current Control ....................85 Pin-shared Functions ........................87 I/O Pin Structures ........................90...
  • Page 5 HT45F8544 BMS Flash MCU Comparator Interrupt .........................141 Programming Considerations ....................141 Serial Interface Module – SIM ................142 SPI Interface ..........................142 C Interface ..........................150 UART Interface ....................160 UART External Pins ........................161 UART Single Wire Mode ......................161 UART Data Transfer Scheme....................161 UART Status and Control Registers..................162...
  • Page 6 HT45F8544 BMS Flash MCU Voltage Spike Suppression Method ..................192 Thermal Consideration ......................193 Application Circuits ..................194 3S Li-Battery Application Circuit ....................194 5S Li-Battery Application Circuit ....................194 8S Li-Battery Application Circuit ....................196 Instruction Set ....................197 Introduction ..........................197 Instruction Timing ........................197 Moving and Transferring Data ....................197...
  • Page 7 HT45F8544 BMS Flash MCU Features CPU Features • Operating Voltage =8MHz: 1.8V~5.5V ♦ =12MHz: 2.7V~5.5V ♦ =16MHz: 3.3V~5.5V ♦ • Up to 0.25μs instruction cycle with 16MHz system clock at V • Power down and wake-up functions to reduce power consumption •...
  • Page 8 HT45F8544 BMS Flash MCU • Direct High Voltage Wake-up function • Package type: 28-pin SSOP General Description The device is a Flash Memory BMS 8-bit high performance RISC architecture microcontroller with an integrated accumulative cell voltage monitor module, designed for BMS applications.
  • Page 9 HT45F8544 BMS Flash MCU Block Diagram Pin-Shared Reset With Port A Circuit BGREF 4K × 16 256 × 8 Pin-Shared VREFI With Port C INT0~ Interrupt EEPROM Stack INT1 Controller 128 × 8 8-level VREF Watchdog Pin- Shared LVD/LVR With Port A...
  • Page 10 2. The OCDSDA and OCDSCK pins are used as the OCDS dedicated pins and only available for the HT45V8544 device which is the OCDS EV chip of the HT45F8544. 3. For the unbounded pins, PB0~PB1, PB4 and PC3~PC6, which should be properly configured to avoid unwanted current consumption resulting from floating input conditions.
  • Page 11 HT45F8544 BMS Flash MCU Pin Name Function Description PAS1 PAWU CMOS General purpose I/O. Register enabled pull-high and wake-up PAPU PA5/AN4/ PAS1 — A/D Converter analog input channel 4 VREFI/VOUT VREFI PAS1 — A/D Converter reference voltage input pin 8 to 1 analog multiplexer output. It is necessary to connect a...
  • Page 12 HT45F8544 BMS Flash MCU Pin Name Function Description Battery cell 4 positive terminal and battery cell 5 negative VBAT4 VBAT4 — — terminal Battery cell 5 positive terminal and battery cell 6 negative VBAT5 VBAT5 — — terminal Battery cell 6 positive terminal and battery cell 7 negative...
  • Page 13 HT45F8544 BMS Flash MCU Absolute Maximum Ratings Supply Voltage (V ) ....................V -0.3V to 5.5V ........................-0.3V to 48.0V HVWK Δ[V ], i=8~2 ....................-0.3V to 5.5V BATi BAT(i-1) ......................-0.3V to 5.5V BAT1 Input Voltage ..................... V -0.3V to V +0.3V...
  • Page 14 HT45F8544 BMS Flash MCU Operating Current Characteristics Ta=25°C Test Conditions Symbol Operation Mode Min. Typ. Max. Unit Conditions 1.8V — SLOW Mode – LIRC =32kHz — μA — 1.8V — =8MHz — — 2.7V — FAST Mode – HIRC =12MHz —...
  • Page 15 HT45F8544 BMS Flash MCU Test Conditions Max. Symbol Operation Mode Min. Typ. Max. Unit @85°C Conditions 1.8V — on, f =8MHz — μA — 1000 1200 2.7V — IDLE1 Mode – HIRC on, f =12MHz — μA — 1800 2000 2200 3.3V...
  • Page 16 HT45F8544 BMS Flash MCU Note: 1. The 3V/5V values for V are provided as these are the two selectable fixed voltages at which the HIRC frequency is trimmed by the writer. 2. The row below the 3V/5V trim voltage row is provided to show the values for the full V range operating voltage.
  • Page 17 HT45F8544 BMS Flash MCU System Start Up Time Characteristics Ta=-40°C~85°C Test Conditions Symbol Parameter Min. Typ. Max. Unit Conditions — /64, f — — System Start-up Time — /64, f — — HIRC HIRC Wake-up from Condition where f is off —...
  • Page 18 HT45F8544 BMS Flash MCU Test Conditions Symbol Parameter Min. Typ. Max. Unit Conditions 3V V =0.9V -0.7 -1.5 — SLEDCn[m+1:m]=00B -1.5 -2.9 — (n=0, 1; m=0, 2, 4, 6) 3V V =0.9V -1.3 -2.5 — SLEDCn[m+1:m]=01B -2.5 -5.1 — (n=0, 1; m=0, 2, 4, 6)
  • Page 19 HT45F8544 BMS Flash MCU A/D Converter Electrical Characteristics Ta=-40°C~85°C Test Conditions Symbol Parameter Min. Typ. Max. Unit Conditions Input Voltage — — — Reference Voltage — — — Resolution — — — — SAINS[3:0]=0000B, SAVRS[1:0]=00B, =2.0μs ADCK 1.8V SAINS[3:0]=0000B, SAVRS[1:0]=00B, =10μs...
  • Page 20 HT45F8544 BMS Flash MCU Test Conditions Symbol Parameter Min. Typ. Max. Unit Conditions Conversion Time (Includes A/D Sample — — — — ADCK and Hold Time) A/D Converter On-to-Start Time — — — — μs ON2ST No load, PGAIS=1, 2.2V —...
  • Page 21 HT45F8544 BMS Flash MCU Test Conditions Unit Symbol Parameter Min. Typ. Max. Conditions Additional Current for LVR Enable 5V LVD disable — — μA Additional Current for LVD Enable 5V LVR disable — — μA Reference Voltage Electrical Characteristics Ta=-40°C~85°C, unless otherwise specified.
  • Page 22 HT45F8544 BMS Flash MCU 3. Load Condition: C =50pF. LOAD Load Condition LOAD Voltage Regulator Electrical Characteristics =36V, C =4.7μF, C =2.2nF and Ta=25 C, unless otherwise specified. Symbol Parameter Test Condition Min. Typ. Max. Unit Supply and Input Supply Voltage —...
  • Page 23 HT45F8544 BMS Flash MCU Accumulative Cell Voltage Monitor Electrical Characteristics =36V, C =4.7μF, C =2.2nF and Ta=25 C, unless otherwise specified. Symbol Parameter Test Condition Min. Typ. Max. Unit Cell Voltage Range i=1~8 — =4.2V×i, i=1~8, PD0=0, BATi Cell Input Leakage Current -0.1...
  • Page 24 HT45F8544 BMS Flash MCU C Electrical Characteristics Ta=25°C Test Conditions Symbol Parameter Min. Typ. Max. Unit Conditions No clock debounce — — C Standard Mode (100kHz) f — 2 system clock debounce — — Frequency (Note) 4 system clock debounce —...
  • Page 25 Time System Architecture A key factor in the high-performance features of the Holtek range of microcontrollers is attributed to their internal system architecture. The device takes advantage of the usual features found within RISC microcontrollers providing increased speed of operation and enhanced performance. The...
  • Page 26 HT45F8544 BMS Flash MCU (System Clock) Phase Clock T1 Phase Clock T2 Phase Clock T3 Phase Clock T4 Program Counter PC+1 PC+2 Fetch Inst. (PC) Pipelining Execute Inst. (PC-1) Fetch Inst. (PC+1) Execute Inst. (PC) Fetch Inst. (PC+2) Execute Inst. (PC+1) System Clocking and Pipelining Fetch Inst.
  • Page 27 HT45F8544 BMS Flash MCU Stack This is a special part of the memory which is used to save the contents of the Program Counter only. The stack is organized into 8 levels and neither part of the data nor part of the program space, and is neither readable nor writeable.
  • Page 28 HT45F8544 BMS Flash MCU Flash Program Memory The Program Memory is the location where the user code or program is stored. For this device the Program Memory is Flash type, which means it can be programmed and re-programmed a large number of times, allowing the user the convenience of code modification on the same device.
  • Page 29 HT45F8544 BMS Flash MCU Program Memory Last Page or TBHP Register Data 16 bits TBLP Register User Selected Register TBLH Register High Byte Low Byte Table Program Example The following example shows how the table pointer and table data is defined and retrieved from the microcontroller.
  • Page 30 There is an EV chip named HT45V8544 which is used to emulate the real MCU device named HT45F8544. The EV chip device also provides an “On-Chip Debug” function to debug the real MCU device during the development process. The EV chip and the real MCU device are almost functionally compatible except for “On-Chip Debug”...
  • Page 31 Program Writer or PC. In addition, the IAP interface can also be any type of communication protocol, such as UART, using I/O pins. Regarding the internal firmware, the user can select versions provided by Holtek or create their own. The following section illustrates the procedures regarding how to implement the IAP firmware.
  • Page 32 HT45F8544 BMS Flash MCU Page FARH FARL[7:5] FARL[4:0] 0000 0000 0000 0000 0000 0000 0000 0000 Tag Address 0000 0000 0000 1111 0000 1111 Page Number and Address Selection Write page data to FD0L/FD0H Read data word to FD0H/FD0L (32 words/page)
  • Page 33 HT45F8544 BMS Flash MCU IAP Flash Program Memory Registers There are two address registers, four 16-bit data registers and three control registers. All the registers are located in Sector 0. Read and Write operations to the Flash memory are carried out by 16-bit data operations using the address and data registers and the control register.
  • Page 34 HT45F8544 BMS Flash MCU • FD0H Register Name Bit 7~0 D15~D8: The first Flash Memory data bit 15~bit 8 Note that when 8-bit data is written into the high byte data register FD0H, the whole 16 bits of data stored in the FD0H and FD0L registers will simultaneously be loaded into the 16-bit write buffer after which the contents of the Flash memory address register pair, FARH and FARL, will be incremented by one.
  • Page 35 HT45F8544 BMS Flash MCU • FD3H Register Name Bit 7~0 D15~D8: The fourth Flash Memory data bit 15~bit 8 • FC0 Register Name CFWEN FMOD2 FMOD1 FMOD0 FWPEN FRDEN Bit 7 CFWEN: Flash Memory Erase/Write function enable control 0: Flash Memory erase/write function is disabled...
  • Page 36 HT45F8544 BMS Flash MCU Bit 1 FRDEN: Flash Memory read enabled bit 0: Flash Memory read disable 1: Flash Memory read enable This is the Flash Memory Read Enable bit which must be set high before any Flash memory read operations are carried out. Clearing this bit to zero will inhibit Flash memory read operations.
  • Page 37 HT45F8544 BMS Flash MCU Flash Memory Erase/Write Flow It is important to understand the Flash memory Erase/Write flow before the Flash memory contents are updated. Users can refer to the corresponding operation procedures when developing their IAP program to ensure that the flash memory contents are correctly updated.
  • Page 38 HT45F8544 BMS Flash MCU Flash Memory Erase/Write Flow Flash Memory Erase/Write Function Enable Procedure (CFWEN=1) Page Erase Flash Memory Blank Check Page Data=0000h? Flash Memory (Page) Write Procedure Set CLWB bit Verify Page Data Correct? Clear CFWEN bit Disable Flash Memory...
  • Page 39 HT45F8544 BMS Flash MCU Flash Memory Erase/Write Function Enable Procedure The Flash Memory Erase/Write Function Enable Mode is specially designed to prevent the flash memory contents from being wrongly modified. In order to allow users to change the Flash memory data using the IAP control registers, users must first enable the Flash Memory Erase/Write function.
  • Page 40 HT45F8544 BMS Flash MCU Flash Memory Erase/Write Function Enable Procedure FMOD[2:0]=110 Set FWPEN=1 Hardware start a timer Write the following pattern to Flash Data registers FD1L=00h, FD1H=04h FD2L=0Dh, FD2H=09h FD3L=C3h, FD3H=40h Is timer Time-out FWPEN=0? Is pattern correct? CFWEN=1 CFWEN=0...
  • Page 41 HT45F8544 BMS Flash MCU Flash Memory Write Procedure After the Flash memory erase/write function has been successfully enabled as the CFWEN bit is set high, the data to be written into the flash memory can be loaded into the write buffer. The selected flash memory page data should be erased by properly configuring the IAP control registers before the data write procedure is executed.
  • Page 42 HT45F8544 BMS Flash MCU Write Flash Memory Flash Memory Erase/Write Function Enable Procedure Page Erase FMOD[2:0]=001 Set CLWB Bit Set Erase Page Address FARH=xxH, FARL=xxH Write dummy data into FD0H (Tag Address) Tag address Finish ? FWT=1 FWT=0 ? Blank Check with Table...
  • Page 43 HT45F8544 BMS Flash MCU Flash Memory Non-Consecutive Write Description The main difference between Flash Memory Consecutive and Non-Consecutive Write operations is whether the data words to be written are located in consecutive addresses or not. If the data to be written is not located in consecutive addresses the desired address should be re-assigned after a data word is successfully written into the Flash Memory.
  • Page 44 HT45F8544 BMS Flash MCU Write Flash Memory Flash Memory Erase/Write Function Enable Procedure Page Erase FMOD[2:0]=001 Set CLWB Bit Set Erase Page Address FARH=xxH, FARL=xxH Write dummy data into FD0H (Tag Address) Tag address Finish ? FWT=1 FWT=0 ? Blank Check with...
  • Page 45 HT45F8544 BMS Flash MCU Important Points to Note for Flash Memory Write Operations 1. The “Flash Memory Erase/Write Function Enable Procedure” must be successfully activated before the Flash Memory erase/write operation is executed. 2. The Flash Memory erase operation is executed to erase a whole page.
  • Page 46 HT45F8544 BMS Flash MCU Read Flash Memory FMOD[2:0]=011 FRDEN=1 Flash Memory Address: FARH=xxh, FARL=xxh FRD=1 FRD=0 ? Read value: FD0L=xxh, FD0H=xxh Read Finish ? FRDEN=0 Flash Memory Read Procedure Note: 1. When the read operation is successfully activated, all CPU operations will temporarily cease.
  • Page 47 HT45F8544 BMS Flash MCU Data Memory The Data Memory is a volatile area of 8-bit wide RAM internal memory and is the location where temporary information is stored. Categorised into two types, the first of these is an area of RAM, known as the Special Function Data Memory.
  • Page 48 HT45F8544 BMS Flash MCU Data Memory Addressing For the device that supports the extended instructions, there is no Bank Pointer for Data Memory addressing. The desired Sector is pointed by the MP1H or MP2H register and the certain Data Memory address in the selected sector is specified by the MP1L or MP2L register when using indirect addressing access.
  • Page 49 HT45F8544 BMS Flash MCU Sector 0 Sector 1 Sector 0 Sector 1 IAR0 IAR1 PCPU MP1L MP1H SIMC0 SIMC1 TBLP SIMD TBLH SIMC2/SIMA TBHP SIMTOC STATUS VBGRC TB1C IAR2 MFI0 MP2L MFI1 MP2H MFI2 RSTFC SLEDC0 INTEG SLEDC1 INTC0 INTC1...
  • Page 50 HT45F8544 BMS Flash MCU Special Function Register Description Most of the Special Function Register details will be described in the relevant functional section, however several registers require a separate description in this section. Indirect Addressing Registers – IAR0, IAR1, IAR2 The Indirect Addressing Registers, IAR0, IAR1 and IAR2, although having their locations in normal RAM register space, do not actually physically exist as normal registers.
  • Page 51 HT45F8544 BMS Flash MCU Example 2 data .section ´data´ adres1 db ? adres2 db ? adres3 db ? adres4 db ? block db ? code .section at 0 ´code´ org 00h start: mov a, 04h ; setup size of block...
  • Page 52 HT45F8544 BMS Flash MCU Program Counter Low Register – PCL To provide additional program control functions, the low byte of the Program Counter is made accessible to programmers by locating it within the Special Purpose area of the Data Memory. By manipulating this register, direct jumps to other program locations are easily implemented.
  • Page 53 HT45F8544 BMS Flash MCU In addition, on entering an interrupt sequence or executing a subroutine call, the status register will not be pushed onto the stack automatically. If the contents of the status registers are important and if the subroutine can corrupt the status register, precautions must be taken to correctly save it.
  • Page 54 HT45F8544 BMS Flash MCU EEPROM Data Memory This device contains an area of internal EEPROM Data Memory. EEPROM is by its nature a non- volatile form of re-programmable memory, with data retention even when its power supply is removed. By incorporating this kind of data memory, a whole new host of application possibilities are made available to the designer.
  • Page 55 HT45F8544 BMS Flash MCU • EEC Register Name EWERTS EREN MODE WREN RDEN Bit 7 EWERTS: EEPROM Erase time and Write time selection 0: Erase time is 3.2ms (t )/Write time is 2.2ms (t EEER EEWR 1: Erase time is 3.7ms (t )/Write time is 3.0ms (t...
  • Page 56 HT45F8544 BMS Flash MCU This is the Data EEPROM Read Control Bit and when set high by the application program will activate a read cycle. This bit will be automatically reset to zero by the hardware after the read cycle has finished. Setting this bit high will have no effect if the RDEN has not first been set high.
  • Page 57 HT45F8544 BMS Flash MCU is changed from “0” to “1”, the internal page buffer will not be cleared. The EEPROM address lower 4 bits are internally incremented by one following the reception of each dummy data byte in the page erase mode. The EEPROM address higher 3 bits used to specify the desired page location will not be incremented.
  • Page 58 HT45F8544 BMS Flash MCU Page Write Mode Before a page write operation is executed, it is important to ensure that a relevant page erase operation has been successfully executed. The EEPROM page write operation can be executed when the mode selection bit, MODE, is set high. The EEPROM is capable of a 16-byte page write.
  • Page 59 HT45F8544 BMS Flash MCU the global, EEPROM and multi-function interrupts are enabled and the stack is not full, a jump to the associated Multi-function interrupt vector will take place. When the interrupt is serviced only the Multi-function interrupt flag will be automatically reset, the EEPROM interrupt flag must be manually reset by the application program.
  • Page 60 HT45F8544 BMS Flash MCU JMP PAGE_READ_FINISH ; ~~~~ The data length can be up to 16 bytes (End) ~~~~ READ: SET IAR1.0 ; start Read Cycle - set RD bit BACK: SZ IAR1.0 ; check for read cycle end JMP BACK MOV A, EED ; move read data to register MOV READ_DATA, A PAGE_READ_FINISH: CLR IAR1 ; disable EEPROM read function CLR MP1H Erasing a Data Page to the EEPROM − polling method MOV A, 040H ; setup memory pointer low byte MP1L...
  • Page 61 HT45F8544 BMS Flash MCU Writing a Data Byte to the EEPROM – polling method MOV A, 040H ; setup Memory Pointer MP1L MOV MP1L, A ; MP1L points to EEC register MOV A, 01H ; setup Memory Pointer MP1H MOV MP1H, A CLR IAR1.4 ; clear MODE bit, select byte write mode MOV A, EEPROM_ADRES ; user defined address MOV EEA, A MOV A, EEPROM_DATA ; user defined data MOV EED, A CLR EMI SET IAR1.3...
  • Page 62 HT45F8544 BMS Flash MCU Oscillators Various oscillator options offer the user a wide range of functions according to their various application requirements. The flexible features of the oscillator functions ensure that the best optimisation can be achieved in terms of speed and power saving. Oscillator selections and operation are selected through a combination of configuration option and relevant control registers.
  • Page 63 HT45F8544 BMS Flash MCU High Speed Oscillators HXTEN IDLE0 Prescaler HIRCEN HIRC SLEEP Low Speed Oscillator CKS2~CKS0 LIRC IDLE2 SLEEP LIRC System Clock Configurations External Crystal/Ceramic Oscillator – HXT The External Crystal/Ceramic System Oscillator is one of the high frequency oscillator choices, which is selected via a software control bit, FHS.
  • Page 64 As Holtek has provided the device with both high and low speed clock sources and the means to switch between them dynamically, the user can optimise the operation of their microcontroller to achieve the best performance/power ratio.
  • Page 65 HT45F8544 BMS Flash MCU High Speed Oscillators HXTEN IDLE0 Prescaler HIRCEN HIRC SLEEP Low Speed Oscillator CKS2~CKS0 LIRC IDLE2 SLEEP LIRC PSC0 Prescaler 0 Time Base 0 TB0[2:0] CLKSEL0[1:0] PSC1 Prescaler 1 Time Base 1 TB1[2:0] CLKSEL1[1:0] Device Clock Configurations...
  • Page 66 HT45F8544 BMS Flash MCU 2. The f clock can be switched on or off which is controlled by the WDT function being LIRC enabled or disabled in the SLEEP mode. FAST Mode This is one of the main operating modes where the microcontroller has all of its functions operational and where the system clock is provided by one of the high speed oscillators.
  • Page 67 HT45F8544 BMS Flash MCU • SCC Register Name CKS2 CKS1 CKS0 — FHIDEN FSIDEN — — Bit 7~5 CKS2~CKS0: System clock selection 000: f 001: f 010: f 011: f 100: f 101: f 110: f 111: f These three bits are used to select which clock is used as the system clock source. In...
  • Page 68 HT45F8544 BMS Flash MCU When the HIRC oscillator is enabled or the HIRC frequency selection is changed by application program, the clock frequency will automatically be changed after the HIRCF flag is set high. It is recommended that the HIRC frequency selected by these two bits should be same with the frequency determined by the configuration option to achieve the HIRC frequency accuracy specified in the A.C.
  • Page 69 HT45F8544 BMS Flash MCU Operating Mode Switching The device can switch between operating modes dynamically allowing the user to select the best performance/power ratio for the present task in hand. In this way microcontroller operations that do not require high performance can be executed using slower clocks thus requiring less operating current and prolonging battery life in portable applications.
  • Page 70 HT45F8544 BMS Flash MCU FAST Mode CKS2~CKS0 = 111 SLOW Mode FHIDEN=0, FSIDEN=0 HALT instruction is executed SLEEP Mode FHIDEN=0, FSIDEN=1 HALT instruction is executed IDLE0 Mode FHIDEN=1, FSIDEN=1 HALT instruction is executed IDLE1 Mode FHIDEN=1, FSIDEN=0 HALT instruction is executed...
  • Page 71 HT45F8544 BMS Flash MCU Entering the SLEEP Mode There is only one way for the device to enter the SLEEP Mode and that is to execute the “HALT” instruction in the application program with both the FHIDEN and FSIDEN bits in the SCC register equal to “0”.
  • Page 72 HT45F8544 BMS Flash MCU • In the status register, the Power Down flag, PDF, will be set and the Watchdog time-out flag, TO, will be cleared. • The WDT will be cleared and resume counting if the WDT function is enabled. If the WDT function is disabled, the WDT will be cleared and then stopped.
  • Page 73 HT45F8544 BMS Flash MCU be immediately serviced, but will rather be serviced later when the related interrupt is finally enabled or when a stack level becomes free. The other situation is where the related interrupt is enabled and the stack is not full, in which case the regular interrupt response takes place. If an interrupt request flag is set high before entering the SLEEP or IDLE Mode, the wake-up function of the related interrupt will be disabled.
  • Page 74 HT45F8544 BMS Flash MCU • RSTFC Register Name — — — — RSTF LVRF — — — — — — — — “x”: unknown Bit 7~4 Unimplemented, read as “0” RSTF: Reset control register software reset flag Bit 3 Described elsewhere.
  • Page 75 HT45F8544 BMS Flash MCU The maximum time out period is when the 2 division ratio is selected. As an example, with a 32kHz LIRC oscillator as its source clock, this will give a maximum watchdog period of around 8 seconds for the 2 division ratio, and a minimum timeout of 8ms for the 2 division ration.
  • Page 76 HT45F8544 BMS Flash MCU 0.9V RSTD Internal Reset Power-On Reset Timing Chart RES Pin Reset As the reset pin is shared with I/O pins, the reset function must be selected using a control register, RSTC. Although the microcontroller has an internal RC reset function, if the VDD power supply rise time is not fast enough or does not stabilise quickly at power-on, the internal reset function may be incapable of providing proper reset operation.
  • Page 77 HT45F8544 BMS Flash MCU There is an internal reset control register, RSTC, which is used to select the external RES pin function and provide a reset when the device operates abnormally due to the environmental noise interference. If the content of the RSTC register is set to any value other than 01010101B or 10101010B, it will reset the device after a delay time, t .
  • Page 78 HT45F8544 BMS Flash MCU Low Voltage Reset – LVR The microcontroller contains a low voltage reset circuit in order to monitor the supply voltage of the device and provides an MCU reset should the value fall below a certain predefined level.
  • Page 79 HT45F8544 BMS Flash MCU • RSTFC Register Name — — — — RSTF LVRF — — — — — — — — “x”: Unknown Bit 7~4 Unimplemented, read as “0” RSTF: Reset control register software reset flag Bit 3 Described elsewhere.
  • Page 80 HT45F8544 BMS Flash MCU Reset Initial Conditions The different types of reset described affect the reset flags in different ways. These flags, known as PDF and TO are located in the status register and are controlled by various microcontroller operations, such as the SLEEP or IDLE Mode function or Watchdog Timer. The reset flags are...
  • Page 81 HT45F8544 BMS Flash MCU Register Reset RES Reset LVR Reset WDT Time-out WDT Time-out Name (Power On) (Normal Operation) (Normal Operation) (Normal Operation) (IDLE/SLEEP) PAPU 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0...
  • Page 82 HT45F8544 BMS Flash MCU Register Reset RES Reset LVR Reset WDT Time-out WDT Time-out Name (Power On) (Normal Operation) (Normal Operation) (Normal Operation) (IDLE/SLEEP) - 1 1 1 1 1 1 1 - 1 1 1 1 1 1 1...
  • Page 83 “-” stands for unimplemented Input/Output Ports Holtek microcontrollers offer considerable flexibility on their I/O ports. With the input or output designation of every pin fully under user program control, pull-high selections for all ports and wake-up selections on certain pins, the user is provided with an I/O structure to meet the needs of a wide range of application possibilities.
  • Page 84 HT45F8544 BMS Flash MCU Note that the pull-high resistor can be controlled by the relevant pull-high control register only when the pin-shared functional pin is selected as a digital input or NMOS output. Otherwise, the pull-high resistors can not be enabled.
  • Page 85 HT45F8544 BMS Flash MCU • PAWU Register Name PAWU7 PAWU6 PAWU5 PAWU4 PAWU3 PAWU2 PAWU1 PAWU0 Bit 7~0 PAWU7~PAWU0: PA7~PA0 wake-up function control 0: Disable 1: Enable I/O Port Control Registers Each I/O port has its own control register known as PAC~PDC, to control the input/output configuration.
  • Page 86 HT45F8544 BMS Flash MCU Register Name SLEDC0 SLEDC07 SLEDC06 SLEDC05 SLEDC04 SLEDC03 SLEDC02 SLEDC01 SLEDC00 SLEDC1 — — SLEDC11 SLEDC10 I/O Port Source Current Control Register List • SLEDC0 Register Name SLEDC07 SLEDC06 SLEDC05 SLEDC04 SLEDC03 SLEDC02 SLEDC01 SLEDC00 SLEDC07~SLEDC06: PB6~PB5 Source Current Selection Bit 7~6 00: Source current=Level 0 (min.)
  • Page 87 HT45F8544 BMS Flash MCU Pin-shared Functions The flexibility of the microcontroller range is greatly enhanced by the use of pins that have more than one function. Limited numbers of pins can force serious design constraints on designers but by supplying pins with multi-functions, many of these difficulties can be overcome. For these pins, the desired function of the multi-function I/O pins is selected by a series of registers via the application program control.
  • Page 88 HT45F8544 BMS Flash MCU Bit 5~4 PAS05~PAS04: PA2 Pin-Shared Function Selection 00: PA2/INT1 01: PA2/INT1 10: PA2/INT1 11: Reserved Bit 3~2 PAS03~PAS02: PA1 Pin-Shared Function Selection 00: PA1/INT0 01: PA1/INT0 10: SDO 11: Reserved Bit 1~0 PAS01~PAS00: PA0 Pin-Shared Function Selection...
  • Page 89 HT45F8544 BMS Flash MCU • PBS1 Register Name — — PBS15 PBS14 PBS13 PBS12 — — — — Bit 7~6 Unimplemented, read as “0” Bit 5~4 PBS15~PBS14: PB6 Pin-Shared function selection 00: PB6 01: SCK/SCL 10: C+ 11: Reserved Bit 3~2...
  • Page 90 HT45F8544 BMS Flash MCU Bit 4 INT0PS: INT0 input source pin selection 0: Reserved 1: PA1 This bit should be kept as “1”. Bit 3 SDI_SDAPS: SDI/SDA input source pin selection 0: Reserved 1: PA3 This bit should be kept as “1”.
  • Page 91 HT45F8544 BMS Flash MCU pins as outputs, these output pins will have an initial high output value unless the associated port data registers are first programmed. Selecting which pins are inputs and which are outputs can be achieved byte-wide by loading the correct values into the appropriate port control register or by programming individual bits in the port control register using the “SET [m].i”...
  • Page 92 HT45F8544 BMS Flash MCU TM Clock Source The clock source which drives the main counter in each TM can originate from various sources. The selection of the required clock source is implemented using the xTCK2~xTCK0 bits in the xTM control registers, where “x” stands for C, S or P type TM. The clock source can be a ratio of...
  • Page 93 HT45F8544 BMS Flash MCU CCR output STM Function Pin Block Diagram Clock input PTCK CCR output PTM Function Pin Block Diagram Programming Considerations The TM Counter Registers and the Compare CCRA and CCRP registers, all have a low and high byte structure.
  • Page 94 HT45F8544 BMS Flash MCU Step 2. Write data to High Byte xTMAH or PTMRPH ♦ – Here data is written directly to the high byte registers and simultaneously data is latched from the 8-bit buffer to the Low Byte registers.
  • Page 95 HT45F8544 BMS Flash MCU Compact Type TM Register Description Overall operation of the Compact TM is controlled using a series of registers. A read only register pair exists to store the internal counter 16-bit value, while a read/write register pair exists to store the internal 16-bit CCRA value.
  • Page 96 HT45F8544 BMS Flash MCU counter will retain its residual value until the bit returns high again. If the CTM is in the Compare Match Output Mode or the PWM Output Mode then the CTM output pin will be reset to its initial condition, as specified by the CTOC bit, when the CTON bit changes from low to high.
  • Page 97 HT45F8544 BMS Flash MCU PWM Output Mode 0: Active low 1: Active high This is the output control bit for the CTM output pin. Its operation depends upon whether CTM is being used in the Compare Match Output Mode or in the PWM Output Mode.
  • Page 98 HT45F8544 BMS Flash MCU • CTMAL Register Name Bit 7~0 D7~D0: CTM CCRA Low Byte Register bit 7 ~ bit 0 CTM 16-bit CCRA bit 7 ~ bit 0 • CTMAH Register Name Bit 7~0 D15~D8: CTM CCRA High Byte Register bit 7 ~ bit 0 CTM 16-bit CCRA bit 15 ~ bit 8 •...
  • Page 99 HT45F8544 BMS Flash MCU Compact Type TM Operating Modes The Compact Type TM can operate in one of three operating modes, Compare Match Output Mode, PWM Output Mode or Timer/Counter Mode. The operating mode is selected using the CTM1 and CTM0 bits in the CTMC1 register.
  • Page 100 HT45F8544 BMS Flash MCU Counter overflow Counter Value CTCCLR = 0; CTM [1:0] = 00 CCRP > 0 CCRP=0 Counter cleared by CCRP value 0xFFFF CCRP > 0 Counter Resume Restart CCRP Pause Stop CCRA Time CTON CTPAU CTPOL CCRP Int.
  • Page 101 HT45F8544 BMS Flash MCU Counter Value CTCCLR = 1; CTM [1:0] = 00 CCRA = 0 CCRA > 0 Counter cleared by CCRA value Counter overflow 0xFFFF CCRA=0 Resume CCRA Pause Stop Counter Restart CCRP Time CTON CTPAU CTPOL No CTMAF flag...
  • Page 102 HT45F8544 BMS Flash MCU Timer/Counter Mode To select this mode, bits CTM1 and CTM0 in the CTMC1 register should be set to “11” respectively. The Timer/Counter Mode operates in an identical way to the Compare Match Output Mode generating the same interrupt flags. The exception is that in the Timer/Counter Mode the CTM output pin is not used.
  • Page 103 HT45F8544 BMS Flash MCU Counter Value CTDPX = 0; CTM [1:0] = 10 Counter cleared by CCRP Counter Reset when CTON returns high CCRP Counter Stop if Pause Resume CTON bit low CCRA Time CTON CTPAU CTPOL CCRA Int. Flag CTMAF CCRP Int.
  • Page 104 HT45F8544 BMS Flash MCU Counter Value CTDPX = 1; CTM [1:0] = 10 Counter cleared by CCRA Counter Reset when CTON returns high CCRA Counter Stop if Pause Resume CTON bit low CCRP Time CTON CTPAU CTPOL CCRP Int. Flag CTMPF CCRA Int.
  • Page 105 HT45F8544 BMS Flash MCU Standard Type TM – STM The Standard Type TM contains four operating modes, which are Compare Match Output, Timer/ Event Counter, Single Pulse Output and PWM Output modes. The Standard TM can also be controlled with one external input pin and can drive one external output pin.
  • Page 106 HT45F8544 BMS Flash MCU Register Name STMC0 STPAU STCK2 STCK1 STCK0 STON — — — STMC1 STM1 STM0 STIO1 STIO0 STOC STPOL STDPX STCCLR STMDL STMDH STMAL STMAH STMRP STRP7 STRP6 STRP5 STRP4 STRP3 STRP2 STRP1 STRP0 16-bit Standard TM Register List •...
  • Page 107 HT45F8544 BMS Flash MCU • STMC1 Register Name STM1 STM0 STIO1 STIO0 STOC STPOL STDPX STCCLR Bit 7~6 STM1~STM0: STM operating mode selection 00: Compare Match Output Mode 01: Undefined 10: PWM Output Mode or Single Pulse Output Mode 11: Timer/Counter Mode These bits setup the required operating mode for the STM.
  • Page 108 HT45F8544 BMS Flash MCU This is the output control bit for the STM output pin. Its operation depends upon whether STM is being used in the Compare Match Output Mode or in the PWM Output Mode/Single Pulse Output Mode. It has no effect if the STM is in the Timer/ Counter Mode.
  • Page 109 HT45F8544 BMS Flash MCU • STMAL Register Name Bit 7~0 D7~D0: STM CCRA Low Byte Register bit 7 ~ bit 0 STM 16-bit CCRA bit 7 ~ bit 0 • STMAH Register Name Bit 7~0 D15~D8: STM CCRA High Byte Register bit 7 ~ bit 0 STM 16-bit CCRA bit 15 ~ bit 8 •...
  • Page 110 HT45F8544 BMS Flash MCU Standard Type TM Operation Modes The Standard Type TM can operate in one of five operating modes, Compare Match Output Mode, PWM Output Mode, Single Pulse Output Mode or Timer/Counter Mode. The operating mode is selected using the STM1 and STM0 bits in the STMC1 register.
  • Page 111 HT45F8544 BMS Flash MCU Counter overflow Counter Value STCCLR = 0; STM [1:0] = 00 CCRP > 0 CCRP=0 Counter cleared by CCRP value 0xFFFF CCRP > 0 Counter Resume Restart CCRP Pause Stop CCRA Time STON STPAU STPOL CCRP Int.
  • Page 112 HT45F8544 BMS Flash MCU Counter Value STCCLR = 1; STM [1:0] = 00 CCRA = 0 CCRA > 0 Counter cleared by CCRA value Counter overflow 0xFFFF CCRA=0 Resume CCRA Pause Stop Counter Restart CCRP Time STON STPAU STPOL No STMAF flag...
  • Page 113 HT45F8544 BMS Flash MCU Timer/Counter Mode To select this mode, bits STM1 and STM0 in the STMC1 register should be set to “11” respectively. The Timer/Counter Mode operates in an identical way to the Compare Match Output Mode generating the same interrupt flags. The exception is that in the Timer/Counter Mode the STM output pin is not used.
  • Page 114 HT45F8544 BMS Flash MCU Counter Value STDPX = 0; STM [1:0] = 10 Counter cleared by CCRP Counter Reset when STON returns high CCRP Counter Stop if Pause Resume STON bit low CCRA Time STON STPAU STPOL CCRA Int. Flag STMAF CCRP Int.
  • Page 115 HT45F8544 BMS Flash MCU Counter Value STDPX = 1; STM [1:0] = 10 Counter cleared by CCRA Counter Reset when STON returns high CCRA Counter Stop if Pause Resume STON bit low CCRP Time STON STPAU STPOL CCRP Int. Flag STMPF CCRA Int.
  • Page 116 HT45F8544 BMS Flash MCU Single Pulse Output Mode To select this mode, bits STM1 and STM0 in the STMC1 register should be set to “10” respectively and also the STIO1 and STIO0 bits should be set to “11” respectively. The Single Pulse Output Mode, as the name suggests, will generate a single shot pulse on the STM output pin.
  • Page 117 HT45F8544 BMS Flash MCU Counter Value STM [1:0] = 10 ; STIO [1:0] = 11 Counter stopped by CCRA Counter Reset when STON returns high CCRA Counter Stops by Resume Pause software CCRP Time STON Software Software Cleared by Software...
  • Page 118 HT45F8544 BMS Flash MCU Periodic Type TM – PTM The Periodic Type TM contains four operating modes, which are Compare Match Output, Timer/ Event Counter, Single Pulse Output and PWM Output modes. The Periodic TM can also be controlled with one external input pin and can drive one external output pin.
  • Page 119 HT45F8544 BMS Flash MCU Register Name PTMC0 PTPAU PTCK2 PTCK1 PTCK0 PTON — — — PTMC1 PTM1 PTM0 PTIO1 PTIO0 PTOC PTPOL PTCCLR PTMDL PTMDH — — — — — — PTMAL PTMAH — — — — — — PTMRPL...
  • Page 120 HT45F8544 BMS Flash MCU • PTMC1 Register Name PTM1 PTM0 PTIO1 PTIO0 PTOC PTPOL PTCCLR Bit 7~6 PTM1~PTM0: PTM operating mode selection 00: Compare Match Output Mode 01: Undefined 10: PWM Output Mode or Single Pulse Output Mode 11: Timer/Counter Mode These bits setup the required operating mode for the PTM.
  • Page 121 HT45F8544 BMS Flash MCU Output Mode/Single Pulse Output Mode. It has no effect if the PTM is in the Timer/ Counter Mode. In the Compare Match Output Mode it determines the logic level of the PTM output pin before a compare match occurs. In the PWM Output Mode it determines if the PWM signal is active high or active low.
  • Page 122 HT45F8544 BMS Flash MCU • PTMAL Register Name Bit 7~0 D7~D0: PTM CCRA Low Byte Register bit 7 ~ bit 0 PTM 10-bit CCRA bit 7 ~ bit 0 • PTMAH Register Name — — — — — — —...
  • Page 123 HT45F8544 BMS Flash MCU Periodic Type TM Operation Modes The Periodic Type TM can operate in one of four operating modes, Compare Match Output Mode, PWM Output Mode, Single Pulse Output Mode or Timer/Counter Mode. The operating mode is selected using the PTM1 and PTM0 bits in the PTMC1 register.
  • Page 124 HT45F8544 BMS Flash MCU Counter overflow Counter Value PTCCLR = 0; PTM [1:0] = 00 CCRP > 0 CCRP=0 Counter cleared by CCRP value 0x3FF CCRP > 0 Counter Resume Restart CCRP Pause Stop CCRA Time PTON PTPAU PTPOL CCRP Int.
  • Page 125 HT45F8544 BMS Flash MCU Counter Value PTCCLR = 1; PTM [1:0] = 00 CCRA = 0 CCRA > 0 Counter cleared by CCRA value Counter overflow 0x3FF CCRA=0 Resume CCRA Pause Stop Counter Restart CCRP Time PTON PTPAU PTPOL No PTMAF flag...
  • Page 126 HT45F8544 BMS Flash MCU Timer/Counter Mode To select this mode, bits PTM1 and PTM0 in the PTMC1 register should be set to “11” respectively. The Timer/Counter Mode operates in an identical way to the Compare Match Output Mode generating the same interrupt flags. The exception is that in the Timer/Counter Mode the PTM output pin is not used.
  • Page 127 HT45F8544 BMS Flash MCU Counter Value PTM [1:0] = 10 Counter cleared by CCRP Counter Reset when PTON returns high CCRP Counter Stop if Pause Resume PTON bit low CCRA Time PTON PTPAU PTPOL CCRA Int. Flag PTMAF CCRP Int.
  • Page 128 HT45F8544 BMS Flash MCU Single Pulse Output Mode To select this mode, bits PTM1 and PTM0 in the PTMC1 register should be set to “10” respectively and also the PTIO1 and PTIO0 bits should be set to “11” respectively. The Single Pulse Output Mode, as the name suggests, will generate a single shot pulse on the PTM output pin.
  • Page 129 HT45F8544 BMS Flash MCU Counter Value PTM [1:0] = 10; PTIO [1:0] = 11 Counter stopped by CCRA Counter Reset when PTON returns high CCRA Counter Stops by Resume Pause software CCRP Time PTON Auto. set by PTCK pin Software...
  • Page 130 HT45F8544 BMS Flash MCU Analog to Digital Converter The need to interface to real world analog signals is a common requirement for many electronic systems. However, to properly process these signals by a microcontroller, they must first be converted into digital signals by A/D converters. By integrating the A/D conversion electronic circuitry into the microcontroller, the need for external components is reduced significantly with the corresponding follow-on benefits of lower costs and reduced component space requirements.
  • Page 131 HT45F8544 BMS Flash MCU A/D Converter Register Description Overall operation of the A/D converter is controlled using a series of registers. A read only register pair exists to store the A/D converter data 12-bit value. Three registers, SADC0, SADC1 and SADC2, are the control registers which setup the operating conditions and control function of the A/D converter.
  • Page 132 HT45F8544 BMS Flash MCU The relevant pin-shared function selection bits determine which pins on I/O ports are used as analog inputs for the A/D converter input and which pins are not to be used as the A/D converter input. When the pin is selected to be an A/D converter input, its original function whether it is an I/O or other pin-shared function will be removed.
  • Page 133 HT45F8544 BMS Flash MCU • SADC1 Register Name SAINS3 SAINS2 SAINS1 SAINS0 — SACKS2 SACKS1 SACKS0 — — Bit 7~4 SAINS3~SAINS0: A/D converter input signal selection 0000: External signal – External analog channel input, ANn 0001: Internal signal – Internal A/D converter power supply voltage AV 0010: Internal signal –...
  • Page 134 HT45F8544 BMS Flash MCU Bit 3~2 SAVRS1~SAVRS0: A/D converter reference voltage selection 00: Internal A/D converter power, AV 01: External VREF pin 1x: Internal PGA output voltage, V These bits are used to select the A/D converter reference voltage source. When the internal reference voltage source is selected, the reference voltage derived from the external VREF pin will automatically be switched off.
  • Page 135 HT45F8544 BMS Flash MCU A/D Converter Input Signals All of the external A/D analog input pins are pin-shared with the I/O pins as well as other functions. The corresponding pin-shared function selection bits in the PxS1 and PxS0 registers, determine whether the external input pins are set as A/D converter analog channel inputs or whether they have other functions.
  • Page 136 HT45F8544 BMS Flash MCU The clock source for the A/D converter, which originates from the system clock f , can be chosen to be either f or a subdivided version of f . The division ratio value is determined by the SACKS2~SACKS0 bits in the SADC1 register.
  • Page 137 HT45F8544 BMS Flash MCU ON2ST ADCEN A/D sampling time A/D sampling time START Start of A/D conversion Start of A/D conversion Start of A/D conversion ADBZ End of A/D End of A/D conversion conversion SACS[3:0] 0011B 0100B 0101B 0110B (SAINS[3:0]=0000B)
  • Page 138 HT45F8544 BMS Flash MCU • Step 9 The A/D conversion procedure can now be initialised by setting the START bit from low to high and then low again. • Step 10 If A/D conversion is in progress, the ADBZ flag will be set high. After the A/D conversion process is completed, the ADBZ flag will go low and then output data can be read from the SADOH and SADOL registers.
  • Page 139 HT45F8544 BMS Flash MCU A/D Conversion Programming Examples The following two programming examples illustrate how to setup and implement an A/D conversion. In the first example, the method of polling the ADBZ bit in the SADC0 register is used to detect when the conversion cycle is complete, whereas in the second example, the A/D converter interrupt is used to determine when the conversion is complete.
  • Page 140 HT45F8544 BMS Flash MCU mov SADOL_buffer,a ; save result to user defined register mov a,SADOH ; read high byte conversion result value mov SADOH_buffer,a ; save result to user defined register EXIT_INT_ISR: mov a,status_stack mov STATUS,a ; restore STATUS from user defined memory mov a,acc_stack ; restore ACC from user defined memory reti Comparator An analog comparator is contained within the device. The comparator function offers flexibility via their register controlled features such as power-down, polarity select, hysteresis etc. In sharing their pins with normal I/O pins the comparators do not waste precious I/O pins if these functions are otherwise unused.
  • Page 141 HT45F8544 BMS Flash MCU • CMPC Register Name — CMPEN CMPPOL CMPO — — — CMPHYEN — — — — — — — — Bit 7 Unimplemented, read as “0” Bit 6 CMPEN: Comparator Enable Control 0: Disable 1: Enable This is the Comparator on/off control bit.
  • Page 142 HT45F8544 BMS Flash MCU Serial Interface Module – SIM The device contains a Serial Interface Module, which includes both the four-line SPI interface or two-line I C interface types, to allow an easy method of communication with external peripheral hardware. Having relatively simple communication protocols, these serial interface types allow...
  • Page 143 HT45F8544 BMS Flash MCU The SPI function in this device offers the following features: • Full duplex synchronous data transfer • Both Master and Slave modes • LSB first or MSB first data transmission modes • Transmission complete flag • Rising or falling active clock edge...
  • Page 144 HT45F8544 BMS Flash MCU • SIMD Register Name “x”: unknown D7~D0: SIM data register bit 7~bit 0 Bit 7~0 SPI Control Registers There are also two control registers for the SPI interface, SIMC0 and SIMC2. Note that the SIMC2 register also has the name SIMA which is used by the I C function.
  • Page 145 HT45F8544 BMS Flash MCU Bit 0 SIMICF: SIM SPI Incomplete Flag 0: SIM SPI conmunication incompleted did not occur 1: SIM SPI conmunication incompleted occurred This bit is only available when the SIM is configured to operate in an SPI slave mode.
  • Page 146 HT45F8544 BMS Flash MCU Bit 1 WCOL: SPI write collision flag 0: No collision 1: Collision The WCOL flag is used to detect if a data collision has occurred. If this bit is high it means that data has been attempted to be written to the SIMD register during a data transfer operation.
  • Page 147 HT45F8544 BMS Flash MCU SCK (CKPOLB=1) SCK (CKPOLB=0) D7/D0 D6/D1 D5/D2 D4/D3 D3/D4 D2/D5 D1/D6 D0/D7 SDI Data Capture Write to SIMD (SDO does not change until first SCK edge) SPI Slave Mode Timing – CKEG=0 SCK (CKPOLB=1) SCK (CKPOLB=0)
  • Page 148 HT45F8544 BMS Flash MCU SPI Transfer Write Data Clear WCOL Master Slave into SIMD Master or Slave WCOL=1? SIM[2:0]=000, 001, SIM[2:0]=101 010, 011 or 100 Transmission completed? Configure CKPOLB, (TRF=1?) CKEG, CSEN and MLS Read Data SIMEN=1 from SIMD Clear TRF...
  • Page 149 HT45F8544 BMS Flash MCU depending upon the clock polarity selection bit CKPOLB in the SIMC2 register. If in Slave Mode the SCK line will be in a floating condition. If the SIMEN bit is low, then the bus will be disabled and SCS, SDI, SDO and SCK will all become I/O pins or the other functions.
  • Page 150 HT45F8544 BMS Flash MCU • Step 5 Check the WCOL bit if set high then a collision error has occurred so return to step 4. If equal to zero then go to the following step. • Step 6 Check the TRF bit or wait for a SPI serial bus interrupt.
  • Page 151 HT45F8544 BMS Flash MCU Data Bus C Data Register C Address Register (SIMD) (SIMA) Address HAAS Address Match– Comparator C Interrupt Direction Control SCL Pin Debounce Data in MSB Shift Register Circuitry SDA Pin Read/Write Slave Data out MSB SIMDEB[1:0] TXAK 8-bit Data Transfer Complete–...
  • Page 152 HT45F8544 BMS Flash MCU C Registers There are three control registers associated with the I C bus, SIMC0, SIMC1 and SIMTOC, one slave address register, SIMA, and one data register, SIMD. Register Name SIMC0 SIM2 SIM1 SIM0 — SIMDEB1 SIMDEB0...
  • Page 153 HT45F8544 BMS Flash MCU C Control Register There are also three control registers for the I C interface, SIMC0, SIMC1 and SIMTOC. The register SIMC0 is used to control the enable/disable function and to select the I C slave mode and debounce time.
  • Page 154 HT45F8544 BMS Flash MCU • SIMC1 Register Name HAAS TXAK IAMWU RXAK Bit 7 HCF: I C Bus data transfer completion flag 0: Data is being transferred 1: Completion of an 8-bit data transfer The HCF flag is the data transfer flag. This flag will be zero when data is being transferred.
  • Page 155 HT45F8544 BMS Flash MCU Bit 0 RXAK: I C bus receive acknowledge flag 0: Slave receives acknowledge flag 1: Slave does not receive acknowledge flag The RXAK flag is the receiver acknowledge flag. When the RXAK flag is “0”, it means that a acknowledge signal has been received at the 9th clock, after 8 bits of data have been transmitted.
  • Page 156 HT45F8544 BMS Flash MCU C Bus Start Signal The START signal can only be generated by the master device connected to the I C bus and not by the slave device. This START signal will be detected by all devices connected to the I C bus.
  • Page 157 HT45F8544 BMS Flash MCU to send a STOP signal to release the I C Bus. The corresponding data will be stored in the SIMD register. If setup as a transmitter, the slave device must first write the data to be transmitted into the SIMD register.
  • Page 158 HT45F8544 BMS Flash MCU Start SIMTOF=1? SET SIMTOEN HAAS=1? CLR SIMTOF HTX=1? SRW=1? RETI Read from SIMD to CLR HTX SET HTX release SCL Line CLR TXAK RETI Dummy read from SIMD Write data to SIMD to to release SCL Line...
  • Page 159 HT45F8544 BMS Flash MCU Start Slave Address C time-out counter start Stop C time-out counter reset on SCL negative transition C Time-out When an I C time-out counter overflow occurs, the counter will stop and the SIMTOEN bit will be cleared to zero and the SIMTOF bit will be set high to indicate that a time-out condition has occurred.
  • Page 160 HT45F8544 BMS Flash MCU UART Interface The device contains an integrated full-duplex or half-duplex asynchronous serial communications UART interface that enables communication with external devices that contain a serial interface. The UART function has many features and can transmit and receive data serially by transferring a frame of data with eight or nine data bits per transmission as well as being able to detect errors when the data is overwritten or incorrectly framed.
  • Page 161 HT45F8544 BMS Flash MCU Transmitter Shift Register (TSR) Receiver Shift Register (RSR) ………………………… RX/TX Pin RX/TX Pin ………………………… TX Pin TXR_RXR Register Buffer Baud Rate TXR_RXR Register Generator Data to be transmitted Data received MCU Data Bus UART Data Transfer Block Diagram – SWM=1...
  • Page 162 HT45F8544 BMS Flash MCU Data to be received by the UART is accepted on the external RX/TX pin, from where it is shifted in, LSB first, to the Receiver Shift Register at a rate controlled by the Baud Rate Generator. When the shift register is full, the data will then be transferred from the shift register to the internal TXR_RXR register, where it is buffered and can be manipulated by the application program.
  • Page 163 HT45F8544 BMS Flash MCU not be set in the case of as overrun. The NF flag can be cleared to zero by a software sequence which will involve a read to the status register USR followed by an access to the TXR_RXR data register.
  • Page 164 HT45F8544 BMS Flash MCU The TXIF flag is the transmit data register empty flag. When this read only flag is “0”, it indicates that the character is not transferred to the transmitter shift register. When the flag is “1”, it indicates that the transmitter shift register has received a character from the TXR_RXR data register.
  • Page 165 HT45F8544 BMS Flash MCU Bit 3 STOPS: Number of Stop bits selection 0: One stop bit format is used 1: Two stop bits format is used This bit determines if one or two stop bits are to be used. When this bit is equal to “1”, two stop bits are used.
  • Page 166 HT45F8544 BMS Flash MCU Bit 5 BRGH: Baud Rate speed selection 0: Low speed baud rate 1: High speed baud rate The bit named BRGH selects the high or low speed mode of the Baud Rate Generator. This bit, together with the value placed in the baud rate register BRG, controls the Baud Rate of the UART.
  • Page 167 HT45F8544 BMS Flash MCU • UCR3 Register The UCR3 register is used to enable the UART Single Wire Mode communication. As the name suggests in the single wire mode the UART communication can be implemented in one single line, RX/TX, together with the control of the RXEN and TXEN bits in the UCR2 register.
  • Page 168 HT45F8544 BMS Flash MCU UCR2 BRGH Bit Baud Rate (BR) /[64×(N+1)] /[16×(N+1)] By programming the BRGH bit which allows selection of the related formula and programming the required value in the BRG register, the required baud rate can be setup. Note that because the actual baud rate is determined using a discrete value, N, placed in the BRG register, there will be an error associated between the actual and requested value.
  • Page 169 HT45F8544 BMS Flash MCU Data, Parity and Stop Bit Selection The format of the data to be transferred is composed of various factors such as data bit length, parity on/off, parity type, address bits and the number of stop bits. These factors are determined by the setup of various bits within the UCR1 register.
  • Page 170 HT45F8544 BMS Flash MCU TX output pin can then be configured as the I/O or other pin-shared function by configuring the corresponding pin-shared control bits. Transmitting Data When the UART is transmitting data, the data is shifted on the TX pin from the shift register, with the least significant bit first.
  • Page 171 HT45F8544 BMS Flash MCU UART Receiver The UART is capable of receiving word lengths of either 8 or 9 bits. If the BNO bit is set, the word length will be set to 9 bits with the MSB being stored in the RX8 bit of the UCR1 register. At the receiver core lies the Receive Serial Shift Register, commonly known as the RSR.
  • Page 172 HT45F8544 BMS Flash MCU the break condition on the line is the next start bit. The break character will be loaded into the buffer and no further data will be received until stop bits are received. It should be noted that the RIDLE read only flag will go high when the stop bits have not yet been received.
  • Page 173 HT45F8544 BMS Flash MCU Framing Error – FERR The read only framing error flag, FERR, in the USR register, is set if a zero is detected instead of stop bits. If two stop bits are selected, both stop bits must be high; otherwise the FERR flag will be set.
  • Page 174 HT45F8544 BMS Flash MCU USR Register UCR2 Register TEIE Transmitter Empty Flag TXIF UART Interrupt TIIE Transmitter Idle Interrupt signal Request Flag Flag TIDLE to MCU Receiver Overrun Flag OERR ADDEN Receiver Data Available RXIF WAKE RX/TX Pin TXRX7 if BNO=0...
  • Page 175 HT45F8544 BMS Flash MCU The UART function contains a receiver RX/TX pin wake-up function, which is enabled or disabled by the WAKE bit in the UCR2 register. If this bit, along with the UART enable bit, UREN, the receiver enable bit, RXEN and the receiver interrupt bit, RIE, are all set when the MCU enters the...
  • Page 176 HT45F8544 BMS Flash MCU 011: 2.7V 100: 3.0V 101: 3.3V 110: 3.6V 111: 4.0V LVD Operation The Low Voltage Detector function operates by comparing the power supply voltage, V , with a pre-specified voltage level stored in the LVDC register. This has a range of between 1.8V and 4.0V.
  • Page 177 HT45F8544 BMS Flash MCU Interrupts Interrupts are an important part of any microcontroller system. When an external event or an internal function such as a Timer Module or an A/D converter requires microcontroller attention, their corresponding interrupt will enforce a temporary suspension of the main program allowing the microcontroller to direct attention to their respective needs.
  • Page 178 HT45F8544 BMS Flash MCU • INTEG Register Name — — — — INT1S1 INT1S0 INT0S1 INT0S0 — — — — — — — — Bit 7~4 Unimplemented, read as “0” Bit 3~2 INT1S1~INT1S0: Interrupt edge control for INT1 pin 00: Disable...
  • Page 179 HT45F8544 BMS Flash MCU • INTC1 Register Name TB0F MF2F MF1F TB0E MF2E MF1E Bit 7 TB0F: Time Base 0 interrupt request flag 0: No request 1: Interrupt request Bit 6 ADF: A/D Converter interrupt request flag 0: No request...
  • Page 180 HT45F8544 BMS Flash MCU Bit 2 SIME: SIM interrupt control 0: Disable 1: Enable Bit 1 INT1E: INT1 interrupt control 0: Disable 1: Enable Bit 0 TB1E: Time Base 1 interrupt control 0: Disable 1: Enable • MFI0 Register Name —...
  • Page 181 HT45F8544 BMS Flash MCU Bit 2 CTMPE: CTM Comparator P match interrupt control 0: Disable 1: Enable Bit 1 PTMAE: PTM Comparator A match interrupt control 0: Disable 1: Enable Bit 0 PTMPE: PTM Comparator P match interrupt control 0: Disable 1: Enable •...
  • Page 182 HT45F8544 BMS Flash MCU subroutine is serviced, all the other interrupts will be blocked, as the global interrupt enable bit, EMI bit will be cleared automatically. This will prevent any further interrupt nesting from occurring. However, if other interrupt requests occur during this interval, although the interrupt will not be immediately serviced, the request flag will still be recorded.
  • Page 183 HT45F8544 BMS Flash MCU be setup as an input by setting the corresponding bit in the port control register. When the interrupt is enabled, the stack is not full and the correct transition type appears on the external interrupt pin, a subroutine call to the external interrupt vector, will take place.
  • Page 184 HT45F8544 BMS Flash MCU Time Base Interrupts The function of the Time Base Interrupt is to provide regular time signal in the form of an internal interrupt. They are controlled by the overflow signals from their respective timer functions. When these happen their respective interrupt request flags, TB0F or TB1F, will be set.
  • Page 185 HT45F8544 BMS Flash MCU • TB0C Register Name TB0ON — — — — TB02 TB01 TB00 — — — — — — — — Bit 7 TB0ON: Time Base 0 Enable Control 0: Disable 1: Enable Bit 6~3 Unimplemented, read as “0”...
  • Page 186 HT45F8544 BMS Flash MCU Serial Interface Module Interrupt The Serial Interface Module Interrupt, also known as the SIM interrupt. A SIM Interrupt request will take place when the SIM Interrupt request flag, SIMF, is set, which occurs when a byte of data...
  • Page 187 HT45F8544 BMS Flash MCU high and is independent of whether the interrupt is enabled or not. Therefore, even though the device is in the SLEEP or IDLE Mode and its system oscillator stopped, situations such as external edge transitions on the external interrupt pins, a low power supply voltage or comparator input change may cause their respective interrupt flag to be set high and consequently generate an interrupt.
  • Page 188 HT45F8544 BMS Flash MCU Accumulative Cell Voltage Monitor The Accumulative Cell Voltage Monitor is designed to monitor an accumulative voltage from 1 to N and outputs the divide-by-N voltage to the analog multiplexer. Each divided accumulative cell voltage from pin VBATn can be observed sequentially and measured by using the internal A/D converter as the V voltage has been connected to the A/D converter channel AN4.
  • Page 189 HT45F8544 BMS Flash MCU PD3, PD2 and PD1 are used to control the p-type switches S1~S8 only if PD0=“1”. The control truth table is shown below. This produces an accumulative cell voltage, VBATn, divided by “n” on VOUT. This accurate ±0.5% voltage divided ratio is designed to minimize any mismatch errors.
  • Page 190 HT45F8544 BMS Flash MCU When the voltage applied on HVWK pin is greater than V (typical value is 4.0V), the WKTH accumulative cell voltage monitor and the voltage regulator cannot enter Sleep Mode, even though PB2=1. Wake up from Sleep Mode The HVWK pin can be used for detecting charger plugged-in, switch turned on, or load connected events.
  • Page 191 HT45F8544 BMS Flash MCU VREG To V 4.7μF 4.7μF HT45F8544 VBAT8 VOUT To AN4 2.2nF VIN and VBATn Spike Suppression Resistors The appropriate VIN and VBATn spike suppression resistors corresponded to R9 and Rn lower the voltage spike and inrush current applied on any I/O pins, which can improve the stability of that provides the power source to the external MCUs.
  • Page 192 HT45F8544 BMS Flash MCU PD[3:1] BAT2 BAT2 4.2V BAT4 BAT1 BAT1 BAT5 BAT3 S8~S1 5S Battery Monitoring Timing ≥ 10ms SCAN SCAN SCAN SCAN PD[3:1] BAT2 BAT2 BAT6 BAT8 BAT4 4.2V BAT5 BAT1 BAT1 BAT7 BAT3 S8~S1 ≥ 5ms WAIT...
  • Page 193 HT45F8544 BMS Flash MCU Most battery-management systems would monitor charge and discharge current to prevent over- current damage. Due to the parasitic inductance on conducting wires and PCB layout connections, large voltage spike may occurs while the MCU controlled MOS rapidly shuts down the charge or discharge current, and this spike may damage the device VBATn or VIN pins.
  • Page 194 PB6/SCK/SCL/C+ 4.7V PA7/PTP/AN6 HT45F8544 28SSOP Note: 1. If less than 8 serial batteries are used, connect the unused VBATn to the highest voltage potential. Do not leave any VBATn pin floating to prevent damage to the device. 2. The bold lines indicate that these connections need to be as short as possible.
  • Page 195 PB6/SCK/SCL/C+ PA7/PTP/AN6 4.7V HT45F8544 28SSOP Note: 1. If less than 8 serial batteries are used, connect the unused VBATn to the highest voltage potential. Do not leave any VBATn pin floating to prevent damage to the device. 2. The bold lines indicate that these connections need to be as short as possible.
  • Page 196 PB6/SCK/SCL/C+ PA7/PTP/AN6 4.7V HT45F8544 28SSOP Note: 1. If less than 8 serial batteries are used, connect the unused VBATn to the highest voltage potential. Do not leave any VBATn pin floating to prevent damage to the device. 2. The bold lines indicate that these connections need to be as short as possible.
  • Page 197 In the case of Holtek microcontroller, a comprehensive and flexible set of over 60 instructions is provided to enable programmers to implement their application with the minimum of programming overheads.
  • Page 198 The standard logical operations such as AND, OR, XOR and CPL all have their own instruction within the Holtek microcontroller instruction set. As with the case of most instructions involving data manipulation, data must pass through the Accumulator which may involve additional programming steps.
  • Page 199 HT45F8544 BMS Flash MCU Instruction Set Summary The instructions related to the data memory access in the following table can be used when the desired data memory is located in Data Memory sector 0. Table Conventions x: Bits immediate data...
  • Page 200 HT45F8544 BMS Flash MCU Mnemonic Description Cycles Flag Affected Data Move MOV A,[m] Move Data Memory to ACC None MOV [m],A Move ACC to Data Memory Note None MOV A,x Move immediate data to ACC None Bit Operation CLR [m].i...
  • Page 201 HT45F8544 BMS Flash MCU Extended Instruction Set The extended instructions are used to support the full range address access for the data memory. When the accessed data memory is located in any data memory sector except sector 0, the extended instruction can be used to directly access the data memory instead of using the indirect addressing access.
  • Page 202 HT45F8544 BMS Flash MCU Mnemonic Description Cycles Flag Affected Branch LSZ [m] Skip if Data Memory is zero Note None LSZA [m] Skip if Data Memory is zero with data movement to ACC Note None LSNZ [m] Skip if Data Memory is not zero...
  • Page 203 HT45F8544 BMS Flash MCU Instruction Definition ADC A,[m] Add Data Memory to ACC with Carry Description The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the Accumulator. Operation ACC ← ACC + [m] + C...
  • Page 204 HT45F8544 BMS Flash MCU ANDM A,[m] Logical AND ACC to Data Memory Description Data in the specified Data Memory and the Accumulator perform a bitwise logical AND operation. The result is stored in the Data Memory. Operation [m] ← ACC “AND” [m]...
  • Page 205 HT45F8544 BMS Flash MCU DAA [m] Decimal-Adjust ACC for addition with result in Data Memory Description Convert the contents of the Accumulator value to a BCD (Binary Coded Decimal) value resulting from the previous addition of two BCD variables. If the low nibble is greater than 9 or if AC flag is set, then a value of 6 will be added to the low nibble.
  • Page 206 HT45F8544 BMS Flash MCU JMP addr Jump unconditionally Description The contents of the Program Counter are replaced with the specified address. Program execution then continues from this new address. As this requires the insertion of a dummy instruction while the new address is loaded, it is a two cycle instruction.
  • Page 207 HT45F8544 BMS Flash MCU Return from subroutine Description The Program Counter is restored from the stack. Program execution continues at the restored address. Operation Program Counter ← Stack Affected flag(s) None RET A,x Return from subroutine and load immediate data to ACC...
  • Page 208 HT45F8544 BMS Flash MCU RLCA [m] Rotate Data Memory left through Carry with result in ACC Description Data in the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces the Carry bit and the original carry flag is rotated into the bit 0. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged.
  • Page 209 HT45F8544 BMS Flash MCU SBC A, x Subtract immediate data from ACC with Carry Description The immediate data and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
  • Page 210 HT45F8544 BMS Flash MCU SIZ [m] Skip if increment Data Memory is 0 Description The contents of the specified Data Memory are first incremented by 1. If the result is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction.
  • Page 211 HT45F8544 BMS Flash MCU SUB A,x Subtract immediate data from ACC Description The immediate data specified by the code is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
  • Page 212 HT45F8544 BMS Flash MCU TABRD [m] Read table (specific page) to TBLH and Data Memory Description The low byte of the program code (specific page) addressed by the table pointer (TBLP and TBHP) is moved to the specified Data Memory and the high byte moved to TBLH.
  • Page 213 HT45F8544 BMS Flash MCU Extended Instruction Definition The extended instructions are used to directly access the data stored in any data memory sections. LADC A,[m] Add Data Memory to ACC with Carry Description The contents of the specified Data Memory, Accumulator and the carry flag are added.
  • Page 214 HT45F8544 BMS Flash MCU LCLR [m] Clear Data Memory Description Each bit of the specified Data Memory is cleared to 0. Operation [m] ← 00H Affected flag(s) None LCLR [m].i Clear bit of Data Memory Description Bit i of the specified Data Memory is cleared to 0.
  • Page 215 HT45F8544 BMS Flash MCU LDECA [m] Decrement Data Memory with result in ACC Description Data in the specified Data Memory is decremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. Operation ACC ←...
  • Page 216 HT45F8544 BMS Flash MCU LRL [m] Rotate Data Memory left Description The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0. Operation [m].(i+1) ← [m].i; (i=0~6) [m].0 ← [m].7 Affected flag(s)
  • Page 217 HT45F8544 BMS Flash MCU LRRA [m] Rotate Data Memory right with result in ACC Description Data in the specified Data Memory is rotated right by 1 bit with bit 0 rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged.
  • Page 218 HT45F8544 BMS Flash MCU LSDZ [m] Skip if decrement Data Memory is 0 Description The contents of the specified Data Memory are first decremented by 1. If the result is 0 the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a three cycle instruction.
  • Page 219 HT45F8544 BMS Flash MCU LSIZA [m] Skip if increment Data Memory is zero with result in ACC Description The contents of the specified Data Memory are first incremented by 1. If the result is 0, the following instruction is skipped. The result is stored in the Accumulator but the specified Data Memory contents remain unchanged.
  • Page 220 HT45F8544 BMS Flash MCU LSWAP [m] Swap nibbles of Data Memory Description The low-order and high-order nibbles of the specified Data Memory are interchanged. Operation [m].3~[m].0 ↔ [m].7~[m].4 Affected flag(s) None LSWAPA [m] Swap nibbles of Data Memory with result in ACC Description The low-order and high-order nibbles of the specified Data Memory are interchanged.
  • Page 221 HT45F8544 BMS Flash MCU LTABRDL [m] Read table (last page) to TBLH and Data Memory Description The low byte of the program code (last page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH.
  • Page 222 HT45F8544 BMS Flash MCU Package Information Note that the package information provided here is for consultation purposes only. As this information may be updated at regular intervals users are reminded to consult the Holtek website the latest version of the Package/Carton Information.
  • Page 223 HT45F8544 BMS Flash MCU 28-pin SSOP (150mil) Outline Dimensions &  " Dimensions in inch Symbol Min. Nom. Max. 0.236 BSC 0.154 BSC 0.008 — 0.012 C’ 0.390 BSC — — 0.069 0.025 BSC 0.004 — 0.010 0.016 — 0.050 0.004...
  • Page 224 HOLTEK disclaims all liability arising from the information and its application. In addition, HOLTEK does not recommend the use of HOLTEK’s products where there is a risk of personal hazard due to malfunction or other reasons. HOLTEK hereby declares that it does not authorise the use of these products in life-saving, life-sustaining or safety critical components.