Tim9/12 Interrupt Enable Register (Timx_Dier); Table 63. Timx Internal Trigger Connection - ST STM32F205 series Reference Manual

General-purpose timers (TIM9 to TIM14)
Bit 3 Reserved, must be kept at reset value.
Bits 2:0 SMS: Slave mode selection
Note: The Gated mode must not be used if TI1F_ED is selected as the trigger input
Note: The clock of the slave timer must be enabled prior to receive events from the master
Slave TIM
TIM9
TIM12
15.4.4

TIM9/12 Interrupt enable register (TIMx_DIER)

Address offset: 0x0C
Reset value: 0x0000
15 14 13
Bits 15:7
Bit 6 TIE: Trigger interrupt enable
Bit 5:3
462/1378
When external signals are selected, the active edge of the trigger signal (TRGI) is linked to
the polarity selected on the external input (see Input control register and Control register
descriptions.
000: Slave mode disabled - if CEN = 1 then the prescaler is clocked directly by the internal
clock
001: Reserved
010: Reserved
011: Reserved
100: Reset mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter
and generates an update of the registers
101: Gated mode - The counter clock is enabled when the trigger input (TRGI) is high. The
counter stops (but is not reset) as soon as the trigger becomes low. Counter starts and stops
are both controlled
110: Trigger mode - The counter starts on a rising edge of the trigger TRGI (but it is not
reset). Only the start of the counter is controlled
111: External clock mode 1 - Rising edges of the selected trigger (TRGI) clock the counter
(TS='100'). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the
Gated mode checks the level of the trigger signal.
timer, and must not be changed on-the-fly while triggers are received from the master
timer.

Table 63. TIMx internal trigger connection

ITR0 (TS = 000)
TIM2_TRGO
TIM4_TRGO
12 11 10 9
Reserved
Reserved, must be kept at reset value.
0: Trigger interrupt disabled.
1: Trigger interrupt enabled.
Reserved, must be kept at reset value.
ITR1 (TS = 001)
TIM3_TRGO
TIM5_TRGO
8 7 6
TIE
rw
RM0033 Rev 8
ITR2 (TS = 010) ITR3 (TS = 011)
TIM10_OC
TIM13_OC
5 4 3 2
CC2IE
Res
rw
RM0033
TIM11_OC
TIM14_OC
1 0
CC1IE UIE
rw rw