Xilinx LogiCORE IP MAC v8.5 Manuals

Manuals and User Guides for Xilinx LogiCORE IP MAC v8.5. We have 1 Xilinx LogiCORE IP MAC v8.5 manual available for free PDF download: User Manual

Xilinx LogiCORE IP MAC v8.5 User Manual (138 pages)

UG144 1-Gigabit Ethernet

Brand: Xilinx | Category: Computer Hardware | Size: 1.75 MB

Revision History
3
Table of Contents
5
Schedule of Figures
9
Schedule of Tables
13
Preface: about this Guide
15
- Guide Contents
  15
- Conventions
  16
  - Typographical
    16
  - Online Document
    17
  - List of Acronyms
    17
Chapter 1: Introduction

19
- About the Core
  19
- Recommended Design Experience
  19
- Additional Core Resources
  19
- Related Xilinx Ethernet Products and Services
  19
- Specifications
  20
- Technical Support
  20
- Feedback
  20
  - GEMAC Core
    20
  - Document
    20
Chapter 2: Core Architecture

21
Chapter 3: Generating the Core

31
- Graphical User Interface
  31
  - Figure 3-1: 1-Gigabit Ethernet MAC Main Screen
    31
  - Address Filter
    32
  - Component Name
    32
  - Management Interface
    32
  - Number of Address Table Entries
    32
  - Physical Interface
    32
- Parameter Values in the XCO File
  32
- Output Generation
  33
Chapter 4: Designing with the Core

35
- General Design Guidelines
  35
Chapter 5: Using the Client Side Data Path

39
- Receiving Inbound Frames
  39
- Transmitting Outbound Frames
  47
Chapter 6: Using Flow Control

53
Chapter 7: Using the Physical Side Interface

61
Chapter 8: Configuration and Status

78
- Chapter 8: Configuration and Status
  80
- Chapter 8: Configuration and Status
  82
Chapter 9: Constraining the Core

93
- Required Constraints
  93
- Chapter 9: Constraining the Core
  94
Chapter 10: Clocking and Resetting

109
- Clocking the Core
  109
  - With Internal GMII
    109
  - With External GMII
    109
  - Figure 10-1: Clock Management Logic with External GMII
    109
  - With RGMII
    110
- Multiple Cores
  110
- Reset Conditions
  112
- Figure 10-4: Clock Management Logic with External RGMII (Multiple Cores)
  112
- Figure 10-5: Reset Circuit for a Single Clock/Reset Domain
  112
Chapter 11: Interfacing to Other Cores

113
Chapter 12: Implementing Your Design

123
- Pre-Implementation Simulation
  123
  - Using the Simulation Model
    123
- Synthesis
  123
  - Xst-Vhdl
    123
  - XST-Verilog
    124
- Implementation
  124
  - Generating the Xilinx Netlist
    124
  - Mapping the Design
    124
- Chapter 12: Implementing Your Design
  124
  - Placing-And-Routing the Design
    125
  - Static Timing Analysis
    125
  - Generating a Bitstream
    125
  - Post-Implementation Simulation
    125
    
    Generating a Simulation Model
    125
    
    Using the Model
    126
  - Other Implementation Information
    126
Appendix A: Using the Client-Side FIFO

127
- Figure A-1: Typical 10 Mbps/100 Mbps/ 1 Gbps Ethernet FIFO Implementation
  127
  - Interfaces
    128
    
    Transmit FIFO
    128
    
    Receive FIFO
    129
  - Overview of Locallink Interface
    130
    
    Data Flow
    130
    
    Figure A-2: Frame Transfer Across Locallink Interface
    130
    
    Figure A-3: Frame Transfer with Flow Control
    130
  - Functional Operation
    131
    
    Clock Requirements
    131
    
    Receive FIFO
    131
    
    Transmit FIFO
    131
    
    Expanding Maximum Frame Size
    132
    
    User Interface Data Width Conversion
    132
Appendix B: Core Verification, Compliance, and Interoperability

133
- Verification by Simulation
  133
- Hardware Verification
  133
Appendix C: Calculating DCM Phase-Shifting

135
- DCM Phase-Shifting
  135
- Finding the Ideal Phase-Shift
  135
Appendix D: Core Latency

137
- Transmit Path Latency
  137
- Receive Path Latency
  137

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Xilinx LogiCORE IP MAC v8.5 Manuals

Xilinx LogiCORE IP MAC v8.5 User Manual (138 pages)

Table of Contents

Chapter 1: Introduction

Chapter 2: Core Architecture

Chapter 3: Generating the Core

Chapter 4: Designing with the Core

Chapter 5: Using the Client Side Data Path

Chapter 6: Using Flow Control

Chapter 7: Using the Physical Side Interface

Chapter 8: Configuration and Status

Chapter 9: Constraining the Core

Chapter 10: Clocking and Resetting

Chapter 11: Interfacing to Other Cores

Chapter 12: Implementing Your Design

Appendix A: Using the Client-Side FIFO

Appendix B: Core Verification, Compliance, and Interoperability

Appendix C: Calculating DCM Phase-Shifting

Appendix D: Core Latency

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