Dcireset Primitive; Special Dci Requirements For Some Banks; Dci Cascading - Xilinx SelectIO 7 Series User Manual

Chapter 1: SelectIO Resources

DCIRESET Primitive

DCIRESET is a Xilinx design primitive that provides the capability to perform a reset of the
DCI controller state machine during normal operation of the design. Unless
DCIUpdateMode is set to Quiet (see
case outlined below related to the use of multi-function pins set to use DCI, for most
situations this primitive should not be required in a design. See UG768: Xilinx 7 Series
FPGA Libraries Guide for HDL Designs for more details on the DCIRESET primitive.

Special DCI Requirements for Some Banks

If any of the multi-function pins in I/O banks 14 or 15 (any device), or banks 11, 12, 17, 18,
20, and 21 (SSI devices only) are assigned DCI I/O standards in the user design, the
DCIRESET primitive should also be included and used in the design. In that case, the
design should pulse the RST input of DCIRESET and then wait for the LOCKED signal to
be asserted prior to using any user input or outputs on these pins with DCI standards. This
is required because these I/O pins ignore the initial DCI calibration that happens during
the normal device initialization.
As a result, if the DCIRESET primitive had not been used and DCIUpdateMode was set to
AsRequired, after those pins become normal I/O pins there would be an indeterministic
delay between the end of configuration and when the DCI calibration algorithm updated
those pins DCI settings. If DCIRESET was not used and DCIUpdateMode was set to Quiet,
these pins would never have their DCI values set. In that case, the Controlled Impedance
DCI I/O standards (such as LVDCI_18) would behave as if in the high-Z state all the time,
and Split Termination DCI I/O standards (such as SSTL15_DCI) would behave as if there
was no internal termination. Including and using the DCIRESET primitive in the design
allows these pins to have DCI I/O standards and to perform without issue.

DCI Cascading

The 7 series FPGA HP I/O banks using DCI I/O standards have the option of deriving the
DCI impedance values from another HP I/O bank. As shown in
control bus is internally distributed throughout the bank to control the impedance of each
I/O.
X-Ref Target - Figure 1-6
With DCI cascading, one I/O bank (the master bank) must have its VRN/VRP pins
connected to external reference resistors. Other I/O banks in the same HP I/O bank
column (slave banks) can use DCI standards with the same impedance as the master bank,
without connecting the VRN/VRP pins on these slave banks to external resistors. DCI
impedance control in cascaded banks is received from the I/O master bank.
22
Send Feedback
From Bank Above
To
Local
Bank
From Bank Below
Figure 1-6: DCI Use within a Bank
www.xilinx.com
DCIUpdateMode Configuration
DCI
7 Series FPGAs SelectIO Resources User Guide
Option) or for the
Figure 1-6, a digital
VRN/VRP
UG471_c1_08_101810
UG471 (v1.10) May 8, 2018