Xilinx SelectIO 7 Series Manuals

Manuals and User Guides for Xilinx SelectIO 7 Series. We have 1 Xilinx SelectIO 7 Series manual available for free PDF download: User Manual

Xilinx SelectIO 7 Series User Manual (188 pages)

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Brand: Xilinx | Category: Computer Hardware | Size: 7 MB

Revision History

2
- Table of Contents
  5
Preface: about this Guide

11
- Guide Contents
  
  11
- Additional Resources
  
  11
Chapter 1: Selectio Resources

13
Chapter 2: Selectio Logic Resources

105
- Introduction
  
  105
- ILOGIC Resources
  
  106
  - Combinatorial Input Path
    109
  - Input DDR Overview (IDDR)
    109
    
    OPPOSITE_EDGE Mode
    109
    
    SAME_EDGE Mode
    110
    
    SAME_EDGE_PIPELINED Mode
    110
  - Input DDR Resources (IDDR)
    111
  - IDDR VHDL and Verilog Templates
    112
  - ILOGIC Timing Models
    113
    
    ILOGIC Timing Characteristics
    113
    
    ILOGIC Timing Characteristics, DDR
    113
- Input Delay Resources (IDELAY)
  
  115
  - IDELAYE2 Primitive
    116
  - IDELAY Ports
    117
  - IDELAY Attributes
    119
  - IDELAY Modes
    120
  - IDELAY Timing
    121
    
    IDELAY VHDL and Verilog Instantiation Template
    123
    
    Stability after an Increment/Decrement Operation
    123
- Idelayctrl
  
  124
  - IDELAYCTRL Overview
    124
    
    IDELAYCTRL Ports
    124
    
    IDELAYCTRL Primitive
    124
    
    IDELAYCTRL Locations
    125
    
    IDELAYCTRL Timing
    125
    
    IDELAYCTRL Usage and Design Guidelines
    126
- OLOGIC Resources
  
  126
  - Combinatorial Output Data and 3-State Control Path
    127
  - Output DDR Overview (ODDR)
    127
    
    OPPOSITE_EDGE Mode
    127
    
    SAME_EDGE Mode
    127
    
    Clock Forwarding
    128
  - Output DDR Primitive (ODDR)
    129
  - ODDR VHDL and Verilog Templates
    129
  - OLOGIC Timing Models
    130
    
    Timing Characteristics
    130
- Output Delay Resources (ODELAY)-Not Available in HR Banks
  
  134
  - ODELAYE2 Primitive
    134
  - ODELAY Ports
    135
  - ODELAY Attributes
    137
  - ODELAY Modes
    138
  - ODELAY Timing
    139
    
    ODELAY VHDL and Verilog Instantiation Template
    141
    
    Stability after an Increment/Decrement Operation
    141
Chapter 3: Advanced Selectio Logic Resources

143
- Introduction
  
  143
- Input Serial-To-Parallel Logic Resources (ISERDESE2)
  
  143
  - ISERDESE2 Primitive (ISERDESE2)
    145
  - ISERDESE2 Ports
    146
    
    Registered Outputs - Q1 to Q8
    146
    
    Bitslip Operation - BITSLIP
    147
    
    Clock Enable Inputs - CE1 and CE2
    147
    
    Combinatorial Output - O
    147
    
    Divided Clock Input - CLKDIV
    148
    
    High-Speed Clock Input - CLK
    148
    
    High-Speed Clock Input - CLKB
    148
    
    Serial Input Data from IOB - D
    148
    
    High-Speed Clock for Strobe-Based Memory Interfaces and Oversampling Mode - OCLK
    149
    
    Reset Input - RST
    149
    
    Serial Input Data from IDELAYE2 - DDLY
    149
    
    Serial Input Data from OSERDESE2 - OFB
    149
  - ISERDESE2 Attributes
    150
    
    DATA_RATE Attribute
    151
    
    DATA_WIDTH Attribute
    151
    
    INTERFACE_TYPE Attribute
    151
    
    NUM_CE Attribute
    152
    
    SERDES_MODE Attribute
    152
  - ISERDESE2 Clocking Methods
    152
    
    NETWORKING Interface Type
    152
    
    MEMORY Interface Type
    153
    
    MEMORY_QDR Interface Type
    153
    
    OVERSAMPLE Interface Type
    153
    
    MEMORY_DDR3 Interface Type
    155
  - ISERDESE2 Width Expansion
    155
    
    Guidelines for Expanding the Serial-To-Parallel Converter Bit Width
    155
  - ISERDESE2 Latencies
    156
  - Dynamic Clock Inversions
    156
  - ISERDESE2 Feedback from OSERDESE2
    156
  - Using D and DDLY in the ISERDESE2
    157
  - ISERDESE2 Timing Model and Parameters
    157
    
    Timing Characteristics
    157
  - ISERDESE2 VHDL and Verilog Instantiation Template
    158
  - BITSLIP Submodule
    158
    
    Bitslip Operation
    158
    
    Bitslip Timing Model and Parameters
    160
- Output Parallel-To-Serial Logic Resources (OSERDESE2)
  
  161
  - Data Parallel-To-Serial Converter
    161
  - 3-State Parallel-To-Serial Conversion
    162
  - OSERDESE2 Primitive
    162
  - OSERDESE2 Ports
    163
    
    Data Path Output - OQ
    163
    
    Output Feedback from OSERDESE2 - OFB
    163
    
    3-State Control Output - TFB
    164
    
    3-State Control Output - TQ
    164
    
    3-State Signal Clock Enable - TCE
    164
    
    Divided Clock Input - CLKDIV
    164
    
    High-Speed Clock Input - CLK
    164
    
    Output Data Clock Enable - OCE
    164
    
    Parallel 3-State Inputs - T1 to T4
    164
    
    Parallel Data Inputs - D1 to D8
    164
    
    Reset Input - RST
    164
  - OSERDESE2 Attributes
    165
    
    DATA_RATE_OQ Attribute
    166
    
    DATA_RATE_TQ Attribute
    166
    
    DATA_WIDTH Attribute
    166
    
    SERDES_MODE Attribute
    166
    
    TRISTATE_WIDTH Attribute
    166
  - OSERDESE2 Clocking Methods
    166
  - OSERDESE2 Width Expansion
    167
    
    Guidelines for Expanding the Parallel-To-Serial Converter Bit Width
    168
  - Output Feedback
    168
  - OSERDESE2 Latencies
    168
    
    DEFAULT Interface Type Latencies
    168
  - OSERDESE2 Timing Model and Parameters
    169
    
    Timing Characteristics of 2:1 SDR Serialization
    170
    
    Timing Characteristics of 8:1 DDR Serialization
    171
    
    Timing Characteristics of 4:1 DDR 3-State Controller Serialization
    172
  - OSERDESE2 VHDL and Verilog Instantiation Templates
    173
- IO_FIFO Overview
  
  173
  - In_Fifo
    174
    
    IN_FIFO Primitive
    175
  - Out_Fifo
    177
    
    OUT_FIFO Primitive
    178
  - Resetting the IO_FIFO
    180
  - EMPTY and FULL Flags
    180
  - ALMOST EMPTY and ALMOST FULL Flags
    180

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Xilinx SelectIO 7 Series Manuals

Xilinx SelectIO 7 Series User Manual (188 pages)

Table of Contents

Revision History

Preface: about this Guide

Guide Contents

Additional Resources

Chapter 1: Selectio Resources

I/O Tile Overview

New Features

Selectio Resources Introduction

Selectio Resources General Guidelines

Series FPGA DCI-Only Available in the HP I/O Banks

Series FPGA Selectio Primitives

Series FPGA Selectio Attributes/Constraints

Supported I/O Standards and Terminations

Rules for Combining I/O Standards in the same Bank

Simultaneous Switching Outputs

Chapter 2: Selectio Logic Resources

Introduction

ILOGIC Resources

Input Delay Resources (IDELAY)

Idelayctrl

OLOGIC Resources

Output Delay Resources (ODELAY)-Not Available in HR Banks

Chapter 3: Advanced Selectio Logic Resources

Introduction

Input Serial-To-Parallel Logic Resources (ISERDESE2)

Output Parallel-To-Serial Logic Resources (OSERDESE2)

IO_FIFO Overview

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