Xilinx DS610 Datasheet
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Xilinx DS610 Datasheet

Xilinx DS610 Datasheet

Spartan-3a dsp fpga family
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DS610 October 4, 2010
Module 1:
Introduction and Ordering Information
DS610 (v3.0) October 4, 2010
•
Introduction
•
Features
•
Architectural Overview
•
Configuration Overview
•
General I/O Capabilities
•
Supported Packages and Package Marking
•
Ordering Information
Module 2:
Functional Description
DS610 (v3.0) October 4, 2010
The functionality of the Spartan®-3A DSP FPGA family is
described in the following documents.
•
UG331: Spartan-3 Generation FPGA User Guide
•
Clocking Resources
•
Digital Clock Managers (DCMs)
•
Block RAM
•
Configurable Logic Blocks (CLBs)
-
Distributed RAM
-
SRL16 Shift Registers
-
Carry and Arithmetic Logic
•
I/O Resources
•
Programmable Interconnect
•
ISE® Software Design Tools and IP Cores
•
Embedded Processing and Control Solutions
•
Pin Types and Package Overview
•
Package Drawings
•
Powering FPGAs
•
Power Management
•
UG332: Spartan-3 Generation Configuration User Guide
•
Configuration Overview
•
Configuration Pins and Behavior
•
Bitstream Sizes
•
Detailed Descriptions by Mode
-
Master Serial Mode using Platform Flash PROM
-
Master SPI Mode using Commodity Serial Flash
-
Master BPI Mode using Commodity Parallel Flash
-
Slave Parallel (SelectMAP) using a Processor
-
Slave Serial using a Processor
-
JTAG Mode
•
ISE iMPACT Programming Examples
•
MultiBoot Reconfiguration
•
Design Authentication using Device DNA
© Copyright 2007–2010 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and
other countries. PCI and PCI-X are trademarks of PCI-SIG and used under license. All other trademarks are the property of their respective owners.
DS610 October 4, 2010
Product Specification
1
Spartan-3A DSP FPGA Family Data Sheet
www.xilinx.com
•
UG431: XtremeDSP™ DSP48A for Spartan-3A DSP
FPGAs User Guide
•
DSP48A Slice Design Considerations
•
DSP48A Architecture Highlights
-
18 x 18-Bit Multipliers
-
48-Bit Accumulator
-
18-bit Pre-Adder
•
DSP48A Application Examples
Module 3:
DC and Switching Characteristics
DS610 (v3.0) October 4, 2010
•
DC Electrical Characteristics
•
Absolute Maximum Ratings
•
Supply Voltage Specifications
•
Recommended Operating Conditions
•
Switching Characteristics
•
I/O Timing
•
Configurable Logic Block (CLB) Timing
•
Digital Clock Manager (DCM) Timing
•
Block RAM Timing
•
XtremeDSP Slice Timing
•
Configuration and JTAG Timing
Module 4:
Pinout Descriptions
DS610 (v3.0) October 4, 2010
•
Pin Descriptions
•
Package Overview
•
Pinout Tables
•
Footprint Diagrams
Product Specification
1

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  • Page 1 Design Authentication using Device DNA © Copyright 2007–2010 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. PCI and PCI-X are trademarks of PCI-SIG and used under license. All other trademarks are the property of their respective owners.
  • Page 2 By convention, one Kb is equivalent to 1,024 bits. © Copyright 2007–2010 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. PCI and PCI-X are trademarks of PCI-SIG and used under license. All other trademarks are the property of their respective owners.

  • Page 3: Architectural Overview

    4 or 5 columns in the selected device, as shown in the diagram above. A detailed diagram of the DSP48A can be found in UG431: XtremeDSP DSP48A for Spartan-3A DSP FPGAs User Guide. DS610 (v3.0) October 4, 2010 Product Specification Spartan-3A DSP FPGA Family: Introduction and Ordering Information •...
  • Page 4 The differential (Diff) input-only pin count includes both differential pairs on input-only pins and differential pairs on I/O pins within I/O banks that are restricted to differential inputs. DS610 (v3.0) October 4, 2010 Product Specification Spartan-3A DSP FPGA Family: Introduction and Ordering Information...

  • Page 5: Ordering Information

    The low-power option (LI) is exclusively available in the CS(G)484 package and industrial temperature range. See DS705, XA Spartan-3A DSP Automotive FPGA Family Data Sheet for the XA Automotive Spartan-3A DSP FPGAs. DS610 (v3.0) October 4, 2010 Product Specification Spartan-3A DSP FPGA Family: Introduction and Ordering Information...

  • Page 6: Revision History

    VEHICLE, UNLESS THERE IS A FAIL-SAFE OR REDUNDANCY FEATURE (WHICH DOES NOT INCLUDE USE OF SOFTWARE IN THE XILINX DEVICE TO IMPLEMENT THE REDUNDANCY) AND A WARNING SIGNAL UPON FAILURE TO THE OPERATOR, OR (III) USES THAT COULD LEAD TO DEATH OR PERSONAL INJURY. CUSTOMER ASSUMES THE SOLE RISK AND LIABILITY OF ANY USE OF XILINX PRODUCTS IN SUCH APPLICATIONS.
  • Page 7 Design Authentication using Device DNA © Copyright 2007–2010 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. PCI and PCI-X are trademarks of PCI-SIG and used under license. All other trademarks are the property of their respective owners.
  • Page 8 VEHICLE, UNLESS THERE IS A FAIL-SAFE OR REDUNDANCY FEATURE (WHICH DOES NOT INCLUDE USE OF SOFTWARE IN THE XILINX DEVICE TO IMPLEMENT THE REDUNDANCY) AND A WARNING SIGNAL UPON FAILURE TO THE OPERATOR, OR (III) USES THAT COULD LEAD TO DEATH OR PERSONAL INJURY. CUSTOMER ASSUMES THE SOLE RISK AND LIABILITY OF ANY USE OF XILINX PRODUCTS IN SUCH APPLICATIONS.

  • Page 9: Dc Electrical Characteristics

    Guidelines for Pb-Free Packages. © Copyright 2007–2010 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. PCI and PCI-X are trademarks of PCI-SIG and used under license. All other trademarks are the property of their respective owners.

  • Page 10: Power Supply Specifications

    CMOS Configuration Latch (CCL) and RAM data DRINT CCINT level required to retain CMOS Configuration Latch (CCL) and RAM data DRAUX CCAUX DS610 (v3.0) October 4, 2010 Product Specification Spartan-3A DSP FPGA Family: DC and Switching Characteristics Description supply CCINT...
  • Page 11 For single-ended signals that are placed on a differential-capable I/O, V between the two pins. See Parasitic Leakage in UG331, Spartan-3 Generation FPGA User Guide. Measured between 10% and 90% V DS610 (v3.0) October 4, 2010 Product Specification Spartan-3A DSP FPGA Family: DC and Switching Characteristics...
  • Page 12 For single-ended signals that are placed on a differential-capable I/O, V between the two pins. See Parasitic Leakage in UG331, Spartan-3 Generation FPGA User Guide. This parameter is based on characterization. The pull-up resistance R DS610 (v3.0) October 4, 2010 Product Specification Spartan-3A DSP FPGA Family: DC and Switching Characteristics...
  • Page 13 For more accurate estimates for a specific design, use the Xilinx XPower tools. There are two recommended ways to estimate the total power consumption (quiescent plus dynamic) for a specific design: a) The typical estimates, and does not require a netlist of the design.
  • Page 14 2.5V configuration interface, apply 2.5V to the V throughout configuration. For information on PCI IP solutions, see www.xilinx.com/pci. The PCI IOSTANDARD is not supported on input-only pins. The PCIX IOSTANDARD is available and has equivalent characteristics but no PCI-X IP is supported.
  • Page 15 –2 –4 –6 –8 –12 LVCMOS12 –2 –4 –6 DS610 (v3.0) October 4, 2010 Product Specification Spartan-3A DSP FPGA Family: DC and Switching Characteristics Table 11: DC Characteristics of User I/Os Using Single-Ended Standards (Cont’d) Logic Level Characteristics IOSTANDARD Attribute...
  • Page 16 These higher-drive output standards are supported only on FPGA banks 1 and 3. Inputs are unrestricted. See the chapter "Using I/O Resources" in UG331. All standards except for LVPECL and TMDS can have VCCAUX at either 2.5V or 3.3V. Define your VCCAUX level using the CONFIG VCCAUX constraint. DS610 (v3.0) October 4, 2010 Product Specification...
  • Page 17 At any given time, no more than two of the following differential output standards can be assigned to an I/O bank: LVDS_25, RSDS_25, MINI_LVDS_25, PPDS_25 when =2.5V, or LVDS_33, RSDS_33, MINI_LVDS_33, TMDS_33, PPDS_33 when V DS610 (v3.0) October 4, 2010 Product Specification...

  • Page 18: Table Of Contents

    Table 14: Device DNA Identifier Memory Characteristics Symbol Number of READ operations or JTAG ISC_DNA read operations. Unaffected by DNA_CYCLES HOLD or SHIFT operations. DS610 (v3.0) October 4, 2010 Product Specification Spartan-3A DSP FPGA Family: DC and Switching Characteristics Bank 0 and 2 Bank 0...

  • Page 19: Switching Characteristics

    DS610 (v3.0) October 4, 2010 Product Specification Spartan-3A DSP FPGA Family: DC and Switching Characteristics Create a Xilinx user account and sign up to receive automatic e-mail notification whenever this data sheet or the associated user guides are updated. •...
  • Page 20 Input adjustment from Table 22. If the latter is true, add the appropriate Output adjustment from DCM output jitter is included in all measurements. DS610 (v3.0) October 4, 2010 Product Specification Spartan-3A DSP FPGA Family: DC and Switching Characteristics Conditions...
  • Page 21 Input adjustment from the same table. When the hold time is negative, it is possible to change the data before the clock’s active edge. DCM output jitter is included in all measurements. DS610 (v3.0) October 4, 2010 Product Specification Spartan-3A DSP FPGA Family: DC and Switching Characteristics...
  • Page 22 ICLK input of the Input Flip-Flop (IFF) to the point where data must be held at the Input pin. No Input Delay is programmed. DS610 (v3.0) October 4, 2010 Product Specification Spartan-3A DSP FPGA Family: DC and Switching Characteristics DELAY_...
  • Page 23 SAMP capture window of package, I/O standard, I/O placement, DCM usage, and clock buffer. Please consult the an IOB flip-flop. appropriate Xilinx Answer Record for application-specific values. • Answer Record DS610 (v3.0) October 4, 2010 Product Specification Spartan-3A DSP FPGA Family: DC and Switching Characteristics...
  • Page 24 The time it takes for data to travel from IOPID the Input pin to the I output with the input delay programmed DS610 (v3.0) October 4, 2010 Product Specification Spartan-3A DSP FPGA Family: DC and Switching Characteristics Conditions DELAY_VALUE...
  • Page 25 This propagation time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the data Input. When this is true, add the appropriate Input adjustment from DS610 (v3.0) October 4, 2010 Product Specification Spartan-3A DSP FPGA Family: DC and Switching Characteristics...
  • Page 26 0.68 SSTL2_II 0.68 SSTL3_I 0.78 SSTL3_II 0.78 DS610 (v3.0) October 4, 2010 Product Specification Spartan-3A DSP FPGA Family: DC and Switching Characteristics Table 22: Input Timing Adjustments by IOSTANDARD Convert Input Time from LVCMOS25 to the Units Following Signal Standard...
  • Page 27 This time requires adjustment whenever a signal standard other than LVCMOS25 with 12 mA drive and Fast slew rate is assigned to the data Output. When this is true, add the appropriate Output adjustment from DS610 (v3.0) October 4, 2010 Product Specification...
  • Page 28 This time requires adjustment whenever a signal standard other than LVCMOS25 with 12 mA drive and Fast slew rate is assigned to the data Output. When this is true, add the appropriate Output adjustment from DS610 (v3.0) October 4, 2010 Product Specification...
  • Page 29 8 mA 16.71 12 mA 16.67 16 mA 16.22 24 mA 12.11 DS610 (v3.0) October 4, 2010 Product Specification Spartan-3A DSP FPGA Family: DC and Switching Characteristics Table 25: Add the Convert Output Time from Adjustment LVCMOS25 with 12mA Drive...
  • Page 30 8 mA 15.57 12 mA 15.59 16 mA 14.27 24 mA 11.37 DS610 (v3.0) October 4, 2010 Product Specification Spartan-3A DSP FPGA Family: DC and Switching Characteristics (Cont’d) Table 25: Add the Convert Output Time from Adjustment LVCMOS25 with 12mA Drive...

  • Page 31: Mini_Lvds_25

    HSTL_I_18 HSTL_II_18 HSTL_III_18 SSTL18_I SSTL18_II SSTL2_I SSTL2_II –0.05 SSTL3_I SSTL3_II DS610 (v3.0) October 4, 2010 Product Specification Spartan-3A DSP FPGA Family: DC and Switching Characteristics (Cont’d) Table 25: Add the Convert Output Time from Adjustment LVCMOS25 with 12mA Drive Below...
  • Page 32 SSTL18_II SSTL2_I 1.25 SSTL2_II 1.25 SSTL3_I SSTL3_II DS610 (v3.0) October 4, 2010 Product Specification Spartan-3A DSP FPGA Family: DC and Switching Characteristics LVCMOS, LVTTL), then R open connection, and V measurement point (V used at the Output. X-Ref Target - Figure 8 and a 8.

  • Page 33: Blvds_25

    ) at the Output pin is 0 pF for all signal standards. According to the PCI specification. For information on PCI IP solutions, see www.xilinx.com/pci. The PCIX IOSTANDARD is available and has equivalent characteristics but no PCI-X IP is supported.
  • Page 34 A fourth parameter, C , is always zero. The four parameters describe all relevant output test conditions. IBIS models are found in the Xilinx development software as well as at the following link: www.xilinx.com/support/download/index.htm Delays for a given application are simulated according to its specific load conditions as follows: 1.

  • Page 35: Vccaux = 3.3V

    Top, Bottom (Banks 0, 2) Single-Ended Standards LVTTL Slow Fast QuietIO DS610 (v3.0) October 4, 2010 Product Specification Spartan-3A DSP FPGA Family: DC and Switching Characteristics Table 28: Recommended Simultaneously Switching Outputs per V = 3.3V) Package Type Signal Standard...
  • Page 36 (IOSTANDARD) Top, Bottom (Banks 0, 2) LVCMOS25 Slow Fast QuietIO DS610 (v3.0) October 4, 2010 Product Specification Spartan-3A DSP FPGA Family: DC and Switching Characteristics Table 28: Recommended Simultaneously Switching = 3.3V) (Cont’d) Outputs per V Package Type CS484, FG676...
  • Page 37 HSTL_II_18 HSTL_III_18 SSTL18_I SSTL18_II SSTL2_I SSTL2_II SSTL3_I SSTL3_II DS610 (v3.0) October 4, 2010 Product Specification Spartan-3A DSP FPGA Family: DC and Switching Characteristics Table 28: Recommended Simultaneously Switching = 3.3V) (Cont’d) Outputs per V Package Type CS484, FG676 Signal Standard...
  • Page 38 The minimum allowable pulse width, High or Low, to RPW_CLB the CLB’s SR input Notes: The numbers in this table are based on the operating conditions set forth in DS610 (v3.0) October 4, 2010 Product Specification Spartan-3A DSP FPGA Family: DC and Switching Characteristics Description –...
  • Page 39 Hold time of the BX or BY data input after the active transition at SRLDH the CLK input of the shift register Clock Pulse Width Minimum High or Low pulse width at CLK input DS610 (v3.0) October 4, 2010 Product Specification Spartan-3A DSP FPGA Family: DC and Switching Characteristics Description Description www.xilinx.com...
  • Page 40 Frequency of signals distributed on global buffers (all sides) BUFG Notes: The numbers in this table are based on the operating conditions set forth in DS610 (v3.0) October 4, 2010 Product Specification Spartan-3A DSP FPGA Family: DC and Switching Characteristics Description Table www.xilinx.com...
  • Page 41 Clock Frequency Block RAM clock frequency BRAM Notes: The numbers in this table are based on the operating conditions set forth in DS610 (v3.0) October 4, 2010 Product Specification Spartan-3A DSP FPGA Family: DC and Switching Characteristics Description Table www.xilinx.com...
  • Page 42 "Yes" means that the component is in the path. "No" means that the component is being bypassed. “–“ means that no path exists, so it is not applicable. The numbers in this table are based on the operating conditions set forth in DS610 (v3.0) October 4, 2010 Product Specification Spartan-3A DSP FPGA Family: DC and Switching Characteristics...
  • Page 43 "Yes" means that the component is in the path. "No" means that the component is being bypassed. “–“ means that no path exists, so it is not applicable. The numbers in this table are based on the operating conditions set forth in DS610 (v3.0) October 4, 2010 Product Specification Spartan-3A DSP FPGA Family: DC and Switching Characteristics...
  • Page 44 DCM. The CLK2X output reproduces the clock frequency provided on the CLKIN input. CLKIN input jitter beyond these limits might cause the DCM to lose lock. The DCM specifications are guaranteed when both adjacent DCMs are locked. DS610 (v3.0) October 4, 2010 Product Specification Spartan-3A DSP FPGA Family: DC and Switching Characteristics Period jitter is the worst-case deviation from the ideal clock period over a collection of millions of samples.
  • Page 45 DCM’s Reset input to the rising transition at its LOCKED output. When the DCM is locked, the CLKIN and CLKFB signals are in phase DS610 (v3.0) October 4, 2010 Product Specification Spartan-3A DSP FPGA Family: DC and Switching Characteristics Description Device...
  • Page 46 The DCM specifications are guaranteed when both adjacent DCMs are locked. To support double the maximum effective F clock frequency by two as it enters the DCM. DS610 (v3.0) October 4, 2010 Product Specification Spartan-3A DSP FPGA Family: DC and Switching Characteristics...
  • Page 47 CLKFX jitter of “±[1% of CLKFX period + 200]”. Assume the CLKFX output frequency is 100 MHz. The equivalent CLKFX period is 10 ns and 1% of 10 ns is 0.1 ns or 100 ps. According to the data sheet, the maximum jitter is ±[100 ps + 200 ps] = ±300 ps. DS610 (v3.0) October 4, 2010 Product Specification...
  • Page 48 The DCM_DELAY_STEP values are provided at the bottom of Miscellaneous DCM Timing Table 42: Miscellaneous DCM Timing Symbol DCM_RST_PW_MIN Minimum duration of a RST pulse width DS610 (v3.0) October 4, 2010 Product Specification Spartan-3A DSP FPGA Family: DC and Switching Characteristics Description Description CLKIN < 60 MHz CLKIN ≥...
  • Page 49 DNACLKH CLK Low time DNACLKL Notes: The minimum READ pulse width is 5 ns, and the maximum READ pulse width is 10 μs. DS610 (v3.0) October 4, 2010 Product Specification Spartan-3A DSP FPGA Family: DC and Switching Characteristics Description www.xilinx.com Units –...
  • Page 50 Notes: These parameters based on characterization. For information on using the Spartan-3A DSP Suspend feature, see XAPP480: Using Suspend Mode in Spartan-3 Generation FPGAs. DS610 (v3.0) October 4, 2010 Product Specification Spartan-3A DSP FPGA Family: DC and Switching Characteristics Exiting Suspend Mode...
  • Page 51 Power-on reset and the clearing of configuration memory occurs during this period. This specification applies only to the Master Serial, SPI, and BPI modes. For details on configuration, see UG332 DS610 (v3.0) October 4, 2010 Product Specification Spartan-3A DSP FPGA Family: DC and Switching Characteristics 1.0V 2.0V...
  • Page 52 CCLK22 CCLK25 CCLK27 CCLK33 CCLK44 CCLK50 CCLK100 Notes: Set the ConfigRate option value when generating a configuration bitstream. DS610 (v3.0) October 4, 2010 Product Specification Spartan-3A DSP FPGA Family: DC and Switching Characteristics ConfigRate Temperature Setting Range Commercial (power-on value)
  • Page 53 Industrial Time Table 49: Slave Mode CCLK Input Low and High Time Symbol CCLK Low and High time SCCL SCCH DS610 (v3.0) October 4, 2010 Product Specification Spartan-3A DSP FPGA Family: DC and Switching Characteristics ConfigRate Temperature Setting Range Commercial...
  • Page 54 The numbers in this table are based on the operating conditions set forth in For serial configuration with a daisy-chain of multiple FPGAs, the maximum limit is 25 MHz. DS610 (v3.0) October 4, 2010 Product Specification Spartan-3A DSP FPGA Family: DC and Switching Characteristics...
  • Page 55 CCPAR Notes: The numbers in this table are based on the operating conditions set forth in Some Xilinx documents refer to Parallel modes as “SelectMAP” modes. DS610 (v3.0) October 4, 2010 Product Specification Spartan-3A DSP FPGA Family: DC and Switching Characteristics...
  • Page 56 MOSI output valid delay after CCLK falling edge Setup time on DIN data input before CCLK rising edge Hold time on DIN data input after CCLK rising edge DS610 (v3.0) October 4, 2010 Product Specification Spartan-3A DSP FPGA Family: DC and Switching Characteristics Mode input pins M[2:0] and variant select input pins VS[2:0] are sampled when INIT_B goes High.
  • Page 57 FPGA. Subtract additional printed circuit board routing delay as required by the application. DS610 (v3.0) October 4, 2010 Product Specification Spartan-3A DSP FPGA Family: DC and Switching Characteristics Description www.xilinx.com...
  • Page 58 Address A[25:0] outputs valid after CCLK falling edge Setup time on D[7:0] data inputs before CCLK rising edge Hold time on D[7:0] data inputs after CCLK rising edge DS610 (v3.0) October 4, 2010 Product Specification Spartan-3A DSP FPGA Family: DC and Switching Characteristics Mode input pins M[2:0] are sampled when INIT_B goes High.
  • Page 59 The initial BYTE# timing can be extended using an external, appropriately sized pull-down resistor on the FPGA’s LDC2 pin. The resistor value also depends on whether the FPGA’s PUDC_B pin is High or Low. DS610 (v3.0) October 4, 2010 Product Specification...
  • Page 60 The numbers in this table are based on the operating conditions set forth in For details on JTAG, see Chapter 9, “JTAG Configuraton Mode and Boundary-Scan” in UG332: Spartan-3 Generation Configuration User Guide. DS610 (v3.0) October 4, 2010 Product Specification Spartan-3A DSP FPGA Family: DC and Switching Characteristics...

  • Page 61: Revision History

    Added I Table 8 to note potential leakage between pins of a differential pair. Added note 6 to notes 5 and 6 in DS610 (v3.0) October 4, 2010 Product Specification Spartan-3A DSP FPGA Family: DC and Switching Characteristics Revision Table...

  • Page 62: Pin Types

    PROG_B signals. © Copyright 2007–2010 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. PCI and PCI-X are trademarks of PCI-SIG and used under license. All other trademarks are the property of their respective owners.
  • Page 63 XC3SD1800A FG676 XC3SD3400A Notes: Some VREFs are on INPUT pins. See pinout tables for details. DS610 (v3.0) October 4, 2010 Product Specification Spartan-3A DSP FPGA Family: Pinout Descriptions Description assuming that all I/O-, INPUT-, DUAL-, VREF-, and CLK-type pins are used as general-purpose I/O. AWAKE is counted here as a dual-purpose I/O pin.

  • Page 64: Mechanical Drawings

    Electronic versions of the package pinout tables and foot- prints are available for download from the Xilinx® website. Using a spreadsheet program, the data can be sorted and reformatted according to any specific needs. Similarly, the ASCII-text file is easily parsed by most scripting programs.

  • Page 65: Package Thermal Characteristics

    The power dissipated by an FPGA application has implications on package selection and system design. The power consumed by a Spartan-3A DSP FPGA is reported using either the calculator integrated in the Xilinx ISE® development software. Spartan-3A DSP device package offerings. This information is also available using the The junction-to-case thermal resistance (θ...
  • Page 66 I/O pair appear together in the table. The table also shows the pin number for each pin and the pin type, as defined earlier. An electronic version of this package pinout table and footprint diagram is available for download from the Xilinx website at www.xilinx.com/support/documentation/data_sheets/s3a_pin.zip Pinout Table...
  • Page 67 IO_L30P_1/A18 IP_L31N_1 IO_L28N_1 IO_L26P_1/A14 IO_L26N_1/A15 IO_L32N_1 IP_L31P_1/VREF_1 IO_L28P_1 IO_L29N_1/A17 IO_L32P_1 IO_L25N_1/A13 IP_L27P_1 DS610 (v3.0) October 4, 2010 Product Specification Spartan-3A DSP FPGA Family: Pinout Descriptions Table 63: Spartan-3A DSP CS484 Pinout (Cont’d) CS484 Type Bank Ball GCLK GCLK INPUT VCCO...
  • Page 68 IO_L08P_2 IO_L09P_2/VS1 IO_L09N_2/VS0 IO_L12P_2/D7 IP_2/VREF_2 IO_L16N_2/GCLK15 IO_L18P_2/GCLK2 IO_L19N_2 IP_2 IO_L22N_2/DOUT IO_L23P_2 IO_L23N_2 DS610 (v3.0) October 4, 2010 Product Specification Spartan-3A DSP FPGA Family: Pinout Descriptions Table 63: Spartan-3A DSP CS484 Pinout (Cont’d) CS484 Type Bank Ball DUAL INPUT DUAL VREF...
  • Page 69 IO_L11N_3 IO_L14P_3 IO_L05P_3 IO_L05N_3 IO_L10P_3 IO_L10N_3 IO_L14N_3/VREF_3 IP_L16P_3 IP_L16N_3 IP_L12P_3 IP_L12N_3/VREF_3 IO_L19P_3/LHCLK2 DS610 (v3.0) October 4, 2010 Product Specification Spartan-3A DSP FPGA Family: Pinout Descriptions Table 63: Spartan-3A DSP CS484 Pinout (Cont’d) CS484 Type Bank Ball VREF DUAL DUAL DUAL...
  • Page 70 IO_L36P_3 IO_L35N_3 IO_L37N_3 IO_L37P_3 IO_L35P_3 IP_L39P_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 DS610 (v3.0) October 4, 2010 Product Specification Spartan-3A DSP FPGA Family: Pinout Descriptions Table 63: Spartan-3A DSP CS484 Pinout (Cont’d) CS484 Type Bank Ball INPUT VCCO VCCO VCCO...
  • Page 71 VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX DS610 (v3.0) October 4, 2010 Product Specification Spartan-3A DSP FPGA Family: Pinout Descriptions Table 63: Spartan-3A DSP CS484 Pinout (Cont’d) CS484 Type Bank Ball...
  • Page 72 19 VREF are on INPUT pins. Footprint Migration Differences There are no migration footprint differences between the XC3SD1800A and the XC3SD3400A in the CS484 package. DS610 (v3.0) October 4, 2010 Product Specification Spartan-3A DSP FPGA Family: Pinout Descriptions All Possible I/O Pins by Type...
  • Page 73 VCCINT: Internal core supply voltage (+1.2V). VCCAUX: Auxiliary supply voltage Figure 15: CS484 Package Footprint (Top View–Left Half) DS610 (v3.0) October 4, 2010 Product Specification Spartan-3A DSP FPGA Family: Pinout Descriptions Bank 0 PROG_ L30N_0 L28N_0 L25N_0...
  • Page 74 INPUT L16N_2 L18P_2 L22N_2 L19N_2 L23P_2 GCLK15 GCLK2 DOUT Bank 2 Figure 16: CS484 Package Footprint (Top View–Right Half) DS610 (v3.0) October 4, 2010 Product Specification Spartan-3A DSP FPGA Family: Pinout Descriptions INPUT L07N_0 VCCO_0 VCCAUX L02N_0 L07P_0 INPUT INPUT...
  • Page 75 IO_L08P_0 IP_0 IO_L52N_0/PUDC_B IO_L47P_0 IO_L46P_0 IP_0/VREF_0 IO_L35P_0 IO_L27N_0/GCLK9 IP_0 IO_L16P_0 IO_L08N_0 DS610 (v3.0) October 4, 2010 Product Specification Spartan-3A DSP FPGA Family: Pinout Descriptions Table 66: Spartan-3A DSP FG676 Pinout for XC3SD1800A FPGA (Cont’d) FG676 Bank Type Ball GCLK INPUT...
  • Page 76 IO_L38N_0 IO_L36N_0 IO_L33N_0 IO_L29N_0 IO_L28P_0/GCLK10 IO_L26P_0/GCLK6 IO_L23P_0 IO_L19N_0 IO_L18P_0 IO_L15P_0 IO_L14P_0/VREF_0 DS610 (v3.0) October 4, 2010 Product Specification Spartan-3A DSP FPGA Family: Pinout Descriptions Table 66: Spartan-3A DSP FG676 Pinout for XC3SD1800A FPGA (Cont’d) FG676 Type Bank Ball VREF GCLK...
  • Page 77 IP_L24N_1/VREF_1 IO_L17N_1 IO_L17P_1 IO_L14N_1 IO_L26P_1/A4 IO_L26N_1/A5 IO_L27N_1/A7 IO_L27P_1/A6 IO_L22P_1 IO_L22N_1 IO_L25P_1/A2 DS610 (v3.0) October 4, 2010 Product Specification Spartan-3A DSP FPGA Family: Pinout Descriptions Table 66: Spartan-3A DSP FG676 Pinout for XC3SD1800A FPGA (Cont’d) FG676 Type Bank Ball VCCO VCCO...
  • Page 78 IO_L60P_1 IO_L61N_1 IO_L61P_1 IO_L60N_1 IO_L63N_1/A23 IO_L63P_1/A22 IP_L65P_1/VREF_1 IO_L02P_1/LDC1 IO_L02N_1/LDC0 IO_L05P_1 IO_L03P_1/A0 DS610 (v3.0) October 4, 2010 Product Specification Spartan-3A DSP FPGA Family: Pinout Descriptions Table 66: Spartan-3A DSP FG676 Pinout for XC3SD1800A FPGA (Cont’d) FG676 Type Bank Ball INPUT DUAL...
  • Page 79 IO_L48P_2 IO_L52P_2/D0/DIN/MISO IO_L51P_2 IO_L06P_2 IO_L07P_2 IO_L10N_2 IO_L11N_2 IO_L18P_2 IO_L19P_2/VS1 IO_L22P_2/D7 IO_L24N_2/D4 DS610 (v3.0) October 4, 2010 Product Specification Spartan-3A DSP FPGA Family: Pinout Descriptions Table 66: Spartan-3A DSP FG676 Pinout for XC3SD1800A FPGA (Cont’d) FG676 Type Bank Ball INPUT DUAL...
  • Page 80 IP_2 IP_2 IP_2 IP_2 IP_2 IP_2 IP_2/VREF_2 IP_2 IP_2 VCCO_2 VCCO_2 DS610 (v3.0) October 4, 2010 Product Specification Spartan-3A DSP FPGA Family: Pinout Descriptions Table 66: Spartan-3A DSP FG676 Pinout for XC3SD1800A FPGA (Cont’d) FG676 Type Bank Ball AC20 AC21...
  • Page 81 IO_L29P_3 IO_L27N_3 IO_L27P_3 IO_L28P_3 IO_L28N_3 IO_L26N_3 IO_L26P_3 IO_L21N_3 IO_L21P_3 IO_L25N_3 IO_L25P_3 DS610 (v3.0) October 4, 2010 Product Specification Spartan-3A DSP FPGA Family: Pinout Descriptions Table 66: Spartan-3A DSP FG676 Pinout for XC3SD1800A FPGA (Cont’d) FG676 Type Bank Ball VREF VREF...
  • Page 82 IP_L62N_3 IP_L54N_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 DS610 (v3.0) October 4, 2010 Product Specification Spartan-3A DSP FPGA Family: Pinout Descriptions Table 66: Spartan-3A DSP FG676 Pinout for XC3SD1800A FPGA (Cont’d) FG676 Type Bank Ball INPUT INPUT...
  • Page 83 DONE VCCAUX PROG_B VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX DS610 (v3.0) October 4, 2010 Product Specification Spartan-3A DSP FPGA Family: Pinout Descriptions Table 66: Spartan-3A DSP FG676 Pinout for XC3SD1800A FPGA (Cont’d) FG676 Type Bank Ball VCCAUX VCCAUX...
  • Page 84 Maximum I/Os Package I/O Bank Edge Input-Only Right Bottom Left TOTAL Notes: 28 VREF are on INPUT pins. DS610 (v3.0) October 4, 2010 Product Specification Spartan-3A DSP FPGA Family: Pinout Descriptions All Possible I/O Pins by Type INPUT www.xilinx.com DUAL VREF...
  • Page 85 XC3SD3400A device. Please see the Footprint Migration Differences section for more information. Figure 16: FG676 Package Footprint for XC3SD1800A FPGA (Top View–Left Half) DS610 (v3.0) October 4, 2010 Product Specification Spartan-3A DSP FPGA Family: Pinout Descriptions INPUT INPUT PROG_ ∇...
  • Page 86 L28P_2 L36P_2 VREF_2 VREF_2 L37P_2 L39P_2 GCLK2 Bank 2 Figure 17: FG676 Package Footprint for XC3SD1800A FPGA (Top View–Right Half) DS610 (v3.0) October 4, 2010 Product Specification Spartan-3A DSP FPGA Family: Pinout Descriptions INPUT INPUT ∇ ∇ L07N_0 INPUT INPUT...
  • Page 87 Pairs of pins that form a differential I/O pair appear together in the table. pin and the pin type, as defined earlier. An electronic version of this package pinout table and footprint diagram is available for download from the Xilinx website at: www.xilinx.com/support/documentation/data_sheets/s3a_pin.zip.
  • Page 88 IO_L26P_0/GCLK6 IO_L23P_0 IO_L19N_0 IO_L18P_0 IO_L15P_0 IO_L14P_0/VREF_0 IO_L09N_0 IO_L07P_0 IO_L51P_0 IO_L45P_0 IO_L38P_0 DS610 (v3.0) October 4, 2010 Product Specification Spartan-3A DSP FPGA Family: Pinout Descriptions Table 68: Spartan-3A DSP FG676 Pinout for XC3SD3400A FPGA (Cont’d) FG676 Type Bank Ball GCLK GCLK...
  • Page 89 IO_L31N_1/TRDY1/RHCLK3 IO_L31P_1/RHCLK2 IO_L39N_1/A15 IO_L39P_1/A14 IO_L34N_1/RHCLK7 IO_L42P_1/A16 IO_L37N_1 IP_L36N_1 IO_L33N_1/RHCLK5 IP_L32N_1 IP_L32P_1 DS610 (v3.0) October 4, 2010 Product Specification Spartan-3A DSP FPGA Family: Pinout Descriptions Table 68: Spartan-3A DSP FG676 Pinout for XC3SD3400A FPGA (Cont’d) FG676 Type Bank Ball VREF VREF...
  • Page 90 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 IO_L02P_2/M2 IO_L05N_2 DS610 (v3.0) October 4, 2010 Product Specification Spartan-3A DSP FPGA Family: Pinout Descriptions Table 68: Spartan-3A DSP FG676 Pinout for XC3SD3400A FPGA (Cont’d) FG676 Type Bank Ball VREF VREF...
  • Page 91 IP_2/VREF_2 IO_L29P_2 IO_L32P_2/AWAKE IP_2 IO_L33N_2 IO_L40P_2 IO_L41P_2 IO_L44N_2 IO_L45P_2 IO_L01P_2/M1 IO_L08P_2 DS610 (v3.0) October 4, 2010 Product Specification Spartan-3A DSP FPGA Family: Pinout Descriptions Table 68: Spartan-3A DSP FG676 Pinout for XC3SD3400A FPGA (Cont’d) FG676 Type Bank Ball AF23 AF24...
  • Page 92 IO_L56N_3 IO_L61P_3 IO_L38P_3 IO_L38N_3 IO_L42P_3 IO_L51P_3 IO_L48N_3 IO_L48P_3 IO_L36P_3/VREF_3 IO_L36N_3 IO_L37P_3 DS610 (v3.0) October 4, 2010 Product Specification Spartan-3A DSP FPGA Family: Pinout Descriptions Table 68: Spartan-3A DSP FG676 Pinout for XC3SD3400A FPGA (Cont’d) FG676 Type Bank Ball VCCO AB14...
  • Page 93 IO_L07N_3 IO_L09P_3 IO_L11P_3 IO_L07P_3 IO_L06N_3 IO_L06P_3 IP_3/VREF_3 IO_L02N_3 IO_L02P_3 IP_L66P_3 IP_L66N_3/VREF_3 DS610 (v3.0) October 4, 2010 Product Specification Spartan-3A DSP FPGA Family: Pinout Descriptions Table 68: Spartan-3A DSP FG676 Pinout for XC3SD3400A FPGA (Cont’d) FG676 Type Bank Ball INPUT VREF...
  • Page 94 Table 68: Spartan-3A DSP FG676 Pinout for XC3SD3400A FPGA (Cont’d) Bank XC3SD3400A Pin Name DS610 (v3.0) October 4, 2010 Product Specification Spartan-3A DSP FPGA Family: Pinout Descriptions Table 68: Spartan-3A DSP FG676 Pinout for XC3SD3400A FPGA (Cont’d) FG676 Type Bank Ball www.xilinx.com...
  • Page 95 VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT DS610 (v3.0) October 4, 2010 Product Specification Spartan-3A DSP FPGA Family: Pinout Descriptions Table 68: Spartan-3A DSP FG676 Pinout for XC3SD3400A FPGA (Cont’d) FG676 Type Bank Ball VCCINT VCCINT...
  • Page 96 Maximum I/Os Package I/O Bank Edge Input-Only Right Bottom Left TOTAL Notes: 26 VREF are on INPUT pins. DS610 (v3.0) October 4, 2010 Product Specification Spartan-3A DSP FPGA Family: Pinout Descriptions All Possible I/O Pins by Type INPUT www.xilinx.com DUAL VREF...
  • Page 97 XC3SD1800A device. Please see the Footprint Migration Differences section for more information. Figure 17: FG676 Package Footprint for XC3SD3400A FPGA (Top View–Left Half) DS610 (v3.0) October 4, 2010 Product Specification Spartan-3A DSP FPGA Family: Pinout Descriptions VCCO_0 PROG_ ∇ L51P_0...
  • Page 98 L28P_2 L36P_2 VREF_2 VREF_2 L37P_2 L39P_2 GCLK2 Bank 2 Figure 17: FG676 Package Footprint for XC3SD3400A FPGA (Top View–Right Half) DS610 (v3.0) October 4, 2010 Product Specification Spartan-3A DSP FPGA Family: Pinout Descriptions VCCAUX ∇ ∇ L07N_0 INPUT VREF_1 VCCO_0 ∇...
  • Page 99 IP_L44P_1/ VREF_1 IP_L52N_1/ VREF_1 IP_L52P_1 IP_L65N_1 IP_L65P_1/ VREF_1 DS610 (v3.0) October 4, 2010 Product Specification Spartan-3A DSP FPGA Family: Pinout Descriptions Table 70. Migration from the XC3S1400A Spartan-3A device in the for designs migrating between these devices. Spartan-3A DSP XC3SD1800A...
  • Page 100 Migration Recommendations There are multiple pinout differences between the XC3SD1800A and the XC3SD3400A FPGAs in the FG676 package. Please note the differences between the two devices from DS610 (v3.0) October 4, 2010 Product Specification Spartan-3A DSP FPGA Family: Pinout Descriptions...
  • Page 101 06/02/08 Added AB14 in CS484 in 03/11/09 Corrected bank designation for SUSPEND to VCCAUX. 10/04/10 Revision update to match other data sheet modules. DS610 (v3.0) October 4, 2010 Product Specification Spartan-3A DSP FPGA Family: Pinout Descriptions Revision Table Table Table...

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