Registers - Xilinx MicroBlaze Reference Manual

Registers

MicroBlaze has an orthogonal instruction set architecture. It has thirty-two 32-bit general purpose
registers and up to eighteen 32-bit special purpose registers, depending on configured options.
General Purpose Registers
The thirty-two 32-bit General Purpose Registers are numbered R0 through R31. The register file is
reset on bit stream download (reset value is 0x00000000).
Purpose Register and
existing).
Note:
0
Table 2-7: General Purpose Registers (R0-R31)
0:31
0:31
0:31
0:31
0:31
0:31
0:31
Refer to
MicroBlaze Processor Reference Guide
UG081 (v14.7)
Table 2-7
The register file is not reset by the external reset inputs: Reset, MB_Reset and Debug_Rst.
Figure 2-2: R0-R31
Bits Name
R0
R1 through R13
R14
R15
R16
R17
R18 through R31
Table 4-2 for software conventions on general purpose register usage.
www.xilinx.com
Figure 2-2
provides a description of each register and the register reset value (if
↑
R0-R31
Description
Always has a value of zero. Anything written to
R0 is discarded
32-bit general purpose registers
32-bit register used to store return addresses
for interrupts.
32-bit general purpose register. Recommended
for storing return addresses for user vectors.
32-bit register used to store return addresses
for breaks.
If MicroBlaze is configured to support
hardware exceptions, this register is loaded
with the address of the instruction following
the instruction causing the HW exception,
except for exceptions in delay slots that use
BTR instead (see "Branch Target Register
(BTR)"); if not, it is a general purpose register.
R18 through R31 are 32-bit general purpose
registers.
Registers
is a representation of a General
31
Reset Value
0x00000000
-
-
-
-
-
-
Send Feedback
25