Transmit And Receive Logic - Texas Instruments SimpleLink CC2620 Technical Reference Manual

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19.4.1 Transmit and Receive Logic

The transmit logic performs parallel-to-serial conversion on the data read from the TX FIFO. The control
logic outputs the serial bit stream beginning with a start bit and followed by the data bits (LSB first), parity
bit, and the stop bits, according to the programmed configuration in the control registers. See
for details.
The receive logic performs serial-to-parallel conversion on the received bit stream after a valid start pulse
is detected. Overrun, parity, frame error checking, and line-break detection are also performed, and their
status accompanies the data written to the RX FIFO.
19.4.2 Baud-rate Generation
The baud-rate divisor (BRD) is a 22-bit number consisting of a 16-bit integer and a 6-bit fractional part.
The number formed by these two values is used by the baud-rate generator to determine the bit period.
Having a fractional baud-rate divider allows the UART to generate all standard baud rates.
The 16-bit integer is loaded through the UART Integer Baud-Rate Divisor Register (UART:IBRD), and the
6-bit fractional part is loaded with the UART Fractional Baud-Rate Divisor Register (UART:FBRD).
Equation 1 shows the BRD relationship to the system clock.
BRD = BRDI + BRDF = PERDMACLK / (ClkDiv × Baud Rate)
where:
BRDI is the integer part of the BRD,
BRDF is the fractional part, separated by a decimal place
PERDMACLK is the system clock connected to the UART
ClkDiv is 16
The 6-bit fractional number that is loaded into the UART:FBRD DIVFRAC bit field can be calculated by
taking the fractional part of the baud-rate divisor, multiplying it by 64, and adding 0.5 to account for
rounding errors as shown by
UART:FBRD.DIVFRAC = integer (BRDF × 64 + 0.5)
Along with the UART Line Control, High Byte Register (UART:LCRH), the UART_IBRD and the
UART:FBRD registers form an internal 30-bit register. This internal register is updated only when a write
operation to the UART:LCRH register is performed, so a write to the UART:LCRH register must follow any
changes to the BRD for the changes to take effect.
The four possible sequences to update the baud-rate registers are as follows:
• UART:IBRD write, UART:FBRD write, and UART:LCRH write
• UART:FBRD write, UART;IBRD write, and UART:LCRH write
• UART:IBRD write and UART:LCRH write
• UART:FBRD write and UART:LCRH write
19.4.3 Data Transmission
Data received or transmitted is stored in two FIFOs, though the RX FIFO has an extra 4 bits per character
for status information. For transmission, data is written into the TX FIFO. If the UART is enabled, a data
frame starts transmitting with the parameters indicated in the UART:LCRH register. Data continues to
transmit until no data is left in the TX FIFO. The UART Flag Register (UART:FR) BUSY bit is asserted as
soon as data is written to the TX FIFO (that is, if the FIFO is not empty), and remains asserted while data
is transmitting. The BUSY bit is negated only when the TX FIFO is empty, and the last character has
transmitted from the shift register, including the stop bits. The UART can indicate that it is busy even
though the UART may no longer be enabled.
SWCU117C – February 2015 – Revised September 2015
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Figure 19-2. UART Character Frame
UnTX
LSB MSB
1
5-8 data bits
0
n
Parity bit
Start if
Equation 2.
Universal Asynchronous Receivers and Transmitters (UARTS)
Copyright © 2015, Texas Instruments Incorporated
1-2
Stop bits
enabled
Functional Description
Figure 19-2
(1)
(2)
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