Appendix 20: Digital System Clock Distribution Block Diagram - Keysight U8903B User Manual

Appendix 20: Digital System Clock Distribution Block Diagram

The digital system clock distribution block diagram is shown in Figure A-3.
Internal clock
AES Receiver
Master Clock / Frame Sync In
DSI Generator Frame Sync
DSI Generator Bit Clock
PLL = Phase-Locked Loop
Figure A-3
Keysight U8903B User's Guide
PLL
Recovered Master Clock
PLL
Digital system clock distribution block diagram
Appendixes
Generator Reference Clock
Bit Clock
PLL
Master Clock
Sync Clock
PLL
A
565