System Reference Clock - Keysight M9005A User Manual

Getting Started

System Reference Clock

The M9005A provides a 10 MHz clock (PXI_CLK10) and 100 MHz clock
(PXIe_CLK100) to each peripheral slot. The 100 MHz clock is a high speed
LVPECL clock, while the 10 MHz clock is a TTL/CMOS clock. The backplane also
provides a PXIe_SYNC100 signal which asserts a 10 ns pulse which is
synchronous to PXIe_CLK100.
An independent buffer (having a source impedance matched to the backplane
and a skew of less than 250 ps between slots) drives PXI_CLK10 to each
peripheral slot. You can use this common reference clock signal to synchronize
multiple modules in a measurement or control system.
An independent buffer drives PXIe_CLK100 to each peripheral slot. These clocks
are matched in skew to less than 100 ps. The differential pair must be terminated
on the peripheral with LVPECL termination for the buffer to drive PXIe_CLK100 so
that when there is no peripheral or a peripheral that does not connect to
PXIe_CLK100, there is no clock being driven on the pair to that slot. Refer to
Figure 6
Figure 6
An independent buffer drives PXIe_SYNC100 to each peripheral slot. The
differential pair must be terminated on the peripheral with LVPECL termination
for the buffer to drive PXIe_SYNC100 so that when there is no peripheral or a
peripheral that does not connect to PXIe_SYNC100, there is no SYNC100 signal
being driven on the pair to that slot. Refer to
10
for a termination example.
CLK100 +
CLK100 –
CLK100 Termination
M9005A Chassis Backplane Overview
+
–
50 Ω 50 Ω
47 Ω
0.01 µF
Figure 6
Keysight M9005A PXIe Chassis User Guide
for a termination example.