Motorola MPC823e Reference Manual page 1333

order storage access,
B-113
ori,
B-114
oris,
B-115
rfi,
B-116
rlwimi,
B-118
rlwinm,
B-120
rlwnm,
21-20
sample/preload,
B-122
sc,
B-123
slw,
B-124
sraw,
B-125
srawi,
B-126
srw,
B-127
stb,
B-128
stbu,
B-129
stbux,
B-130
stbx,
B-131
sth,
B-132
sthbrx,
B-133
sthu,
B-134
sthux,
B-135
sthx,
B-136
stmw,
8-3
storage control,
storage synchronization,
8-2
string,
B-137
stswi,
B-138
stswx,
B-139
stw,
B-140
stwbrx,
B-141
stwcx,
B-143
stwu,
B-144
stwux,
B-145
stwx,
B-146
subf,
B-147
subfc,
B-148
subfe,
B-149
subfic,
B-150
subfme,
B-151
subfze,
B-152
sync,
8-2
synchronize,
8-1
system call,
8-1
timing list,
B-153
tlbia,
B-154
tlbie,
B-155
tlbsync,
B-156
tw,
B-157
twi,
B-158
xor,
B-159
xori,
B-160
xoris,
instructions (cancelled), compression of,
7-1
instructions, class,
instructions, controlling the flow of,
MOTOROLA
8-3
8-2
20-8
6-5
MPC823e REFERENCE MANUAL
instructions, definitions,
6-2
instructions, flow of,
instructions, invalid and preferred,
6-6
instructions, issuing,
instructions, serializing,
16-266
interdialog gap,
interface, development system
20-20
debug mode support,
20-22
trap enable mode,
interfacing with slow devices,
5-19
interference, reducing,
interference, reduction,
16-266
interframe gap,
internal accesses (definition),
internal arbiter, enabling,
4-3
internal hard reset,
internal hard reset, causes of,
internal memory map register,
4-4
internal soft reset,
interrupt controller
3-6
memory map,
5-28
interrupt generation,
interrupt handler code, notification of restartability,
6-10
interrupt latency, minimal,
interrupt structure (illustration),
interrupt vectors
16-506
encoding,
16-505
generating,
interrupt, conditions for,
interrupt, recovery from,
interrupt, restarting after an,
interrupts
7-7
classes,
12-5
configuring,
CPM interrupt controller,
7-8
definitions,
6-13
external,
16-187
from SCCx,
16-188
handling in SCCs,
16-502
highest priority,
implementation-specific
6-10
breakpoint,
debug port unmaskable,
implementation-specific data TLB error,
implementation-specific data TLB miss,
implementation-specific instruction TLB error,
11-48
implementation-specific instruction TLB miss,
11-47
implementation-specific,
masking sources in the CPM,
memory management unit
implementation specific data TLB error,
Index
7-1
7-1
6-12
20-22
15-67
5-12
15-68
13-42
4-3
3-1
6-13
12-5
6-7
6-8
6-10
16-512
6-10
11-48
11-47
6-10
16-504
Index-15