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MPC823e Instruction Set—sthbrx
sthbrx
Assembler Syntax
BIT
0
1
2
FIELD
31
BIT
16
17
18
FIELD
B
Definition
Operation
Description
B-132
sthbrx
rS,rA,rB
3
4
5
6
7
19
20
21
22
23
Store Half Word Byte-Reverse Indexed
if rA = 0 then b ← 0
b ← (rA)
else
EA ← b + (rB)
MEM(EA, 2) ← rS[24-31] || rS[16-23]
EA is the sum (rA|0) + (rB). The contents of the low-order eight
bits of rS are stored into bits 0–7 of the half word in memory
addressed by EA. The contents of the subsequent low-order
eight bits of rS are stored into bits 8–15 of the half word in
memory addressed by EA.
Other registers altered:
None
POWERPC ARCHITECTURE
LEVEL
UISA
MPC823e REFERENCE MANUAL
8
9
10
11
12
S
24
25
26
27
28
918
SUPERVISOR
OPTIONAL
LEVEL
13
14
15
A
29
30
31
0
FORM
X
MOTOROLA
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