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MPC823e Instruction Set—stmw
stmw
Assembler Syntax
BIT
0
1
2
FIELD
47
BIT
16
17
18
FIELD
Definition
Operation
Description
B-136
stmw
rS,d(rA)
3
4
5
6
7
19
20
21
22
23
d
Store Multiple Word
if rA = 0 then b ← 0
else b ← (rA)
EA ← b + EXTS(d)
r ← rS
do while r ≤ 31
MEM(EA, 4) ← GPR(r)
r ← r + 1
EA ← EA + 4
EA is the sum (rA|0) + d. n = (32 – rS). n consecutive words
starting at EA are stored from the GPRs rS through r31. For
example, if rS = 30, 2 words are stored. EA must be a multiple
of four. If it is not, either the system alignment exception handler
is invoked or the results are boundedly undefined.
Note that this instruction is likely to have a greater latency and
take longer to execute, perhaps much longer, than a sequence
of individual load or store instructions that produce the same
results.
Other registers altered:
None
POWERPC ARCHITECTURE
LEVEL
UISA
MPC823e REFERENCE MANUAL
8
9
10
11
12
S
24
25
26
27
28
SUPERVISOR
OPTIONAL
LEVEL
13
14
15
A
29
30
31
FORM
D
MOTOROLA
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