Motorola MPC823e Reference Manual page 1331

2-9
I2CSDA,
16-468
I2MOD,
20-9
I-address,
9-6
IC_ADR,
9-5
IC_CST,
9-7
IC_DAT,
11-48
icbi,
20-55
ICR,
6-17 20-45
ICTRL,
,
16-266
IDG (definition),
16-144
IDL (definition),
IDL interface
16-145
implementation,
16-144
operation,
programming
16-149
example,
16-148
programming,
idle condition (definition),
IDMA
16-96
buffer descriptors,
16-100
commands,
edge-sensitive mode,
16-90
features,
16-90
interface signals,
level-sensitive mode,
16-102
operand transfers,
16-90
operation,
parameter RAM memory map,
single address mode,
single-buffer burst fly-by mode,
16-101
starting,
16-101
transfers,
IDMA transfers, performing,
16-89
IDMA,
IDMA1 and 2 mask register,
IDMA1 and 2 status register,
16-95 16-110
IDMRx, ,
16-94 16-109
IDSRx, ,
16-266
IFG (definition),
IIR
16-59
applications,
coefficients and sample data buffers,
function descriptor,
16-59
parameter packet,
16-57
IIR,
image sizes, switching between,
3-1 6-18 12-34
IMMR, , ,
implementation
16-145
IDL interface,
SCCx ASYNC HDLC,
implementing a precise exception model,
16-357
IN token,
infra-red encoder/decoder,
initialization
of the control registers,
MOTOROLA
16-201
16-101
16-101
16-92
16-103
16-105
16-91
16-95 16-110
,
16-94 16-109
,
16-57
16-58
19-4
16-273
6-8
16-198
6-24
MPC823e REFERENCE MANUAL
SCCx in UART mode example,
serial communication controllers,
universal serial bus example,
20-9
instruction address,
instruction cache
9-14
coherency,
commands
CACHE DISABLE,
CACHE ENABLE,
INSTRUCTION CACHE BLOCK
INVALIDATE,
INVALIDATE ALL,
LOAD & LOCK,
UNLOCK ALL,
UNLOCK LINE,
9-8
commands,
data path block diagram,
9-15
debug support,
9-1
features,
instruction fetch on a predicted path,
9-9
invalidating,
9-7
operation,
9-12
reading,
9-14
reset,
restoring the state of,
9-14
restrictions,
special purpose control registers,
updating code and memory region attributes,
9-14
9-14
writing,
instruction cache address register,
instruction cache control and status register,
instruction cache data port register,
9-1
instruction cache,
instruction cache, how to disable,
instruction cache, how to enable,
instruction cache, how to inhibit,
instruction execution timing examples,
instruction execution timing,
instruction fetch show cycles,
instruction flow (illustration),
21-19
instruction register,
instruction, long latency,
instructions
B-1
B-7
add,
B-8
addc,
B-9
adde,
B-10
addi,
B-11
addic,
B-12
addic.,
B-13
addis,
B-14
addme,
B-15
addze,
B-16
and,
Index
16-230
16-188
16-378 16-380
,
9-11
9-11
9-9
9-9
9-10
9-11
9-10
9-4
9-8
9-15
9-4
9-6
9-5
9-7
9-11
9-11
9-11
8-4
8-1
20-8
6-3
6-9
Index-13