Motorola MPC823e Reference Manual page 1334

Index
11-48
implementation specific data TLB miss,
47
implementation specific instruction TLB
11-48
error,
memory managment unit
implementation specific instruction TLB
11-47
miss,
16-504
nested,
on a serial interface RAM entry,
order of detection,
6-14
ordering,
17-8
PCMCIA,
6-11
processing, ,
serial peripheral interface,
12-6
SIU sources,
SMC in Transparent mode,
SMC in UART mode,
6-24
system reset,
6-14
types,
7-7
interrupts,
interrupts, generating,
11-51
invalidating the TLB,
2-7
IOIS16_B,
2-5
IORD,
2-5
IOWR,
2-7
IP_B0,
2-7
IP_B1,
2-7
IP_B2,
2-7
IP_B3,
2-7
IP_B4,
2-7 2-8
IP_B5,
,
2-8
IP_B7,
IrDA
4PPM data encoding,
16-291
data link layer,
interaction pulses,
16-292
physical layer,
programming
high-speed example,
low-speed example,
middle-speed example,
16-198
IrDA (definition),
16-290
IrDA high-speed,
16-288
IrDA low-speed,
16-289
IrDA middle-speed,
16-287
IrDA,
16-269
IRLAP (definition),
16-294
IRMODE,
2-4
IRQ0,
2-4
IRQ1,
2-3
IRQ2,
2-3
IRQ3,
2-3
IRQ4,
2-4
IRQ5,
Index-16
16-141
6-14
7-8
16-455
16-425
16-408
6-7
16-290
16-293
16-300
16-297
16-298
MPC823e REFERENCE MANUAL
2-4
IRQ6,
11-
2-4
IRQ7,
16-296
IRSIP,
16-384
ISDN,
isochronous operation,
2-7
IWP0,
2-7
IWP1,
2-7
IWP2,
J
joint test action group,
JTAG (definition),
K
2-12
KAPWR,
keep-alive power,
key register operation,
2-3 13-5
KR, ,
L
2-8
L1RCLKA,
2-8
L1RCLKB,
2-10
L1RQA,
2-11
L1RSYNCA,
2-10
L1RSYNCB,
2-8
L1RXDA,
2-9
L1RXDB,
2-10
L1ST1,
2-10
L1ST3,
2-10
L1ST4,
2-10
L1ST6,
2-10
L1ST7,
2-10
L1ST8,
2-9
L1TCLKA,
2-9
L1TCLKB,
2-11
L1TSYNCA,
2-9
L1TSYNCB,
2-8
L1TXDA,
2-10
L1TXDB,
20-9
L-address,
15-64
LAST bit,
latency, command execution,
latency, interrupt,
18-21
LCCR,
LCD controller
block diagram, general,
color RAM
active four- and eight-bit color mode,
36
four-bit/pixel grayscale mode,
one-bit/pixel monochrome mode,
16-202
21-1
21-1
5-25
,
5-25
5-27
16-13
6-11
18-7
MOTOROLA
18-
18-33
18-30