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MPC823e Instruction Set—sync
sync
Assembler Syntax
BIT
0
1
2
FIELD
31
BIT
16
17
18
FIELD
00000
Definition
Description
B-152
sync
3
4
5
6
7
00000
19
20
21
22
23
Synchronize
The sync instruction provides an ordering function for the effects
of all instructions executed by a given processor. Executing a
sync instruction ensures that all instructions preceding the sync
instruction appear to have completed before the sync instruction
completes, and that no subsequent instructions are initiated by
the processor until after the sync instruction completes. When
the sync instruction completes, all external accesses caused by
instructions preceding the sync instruction will have been
performed with respect to all other mechanisms that access
memory.
Multiprocessor implementations also send a sync address-only
broadcast that is useful in some designs. For example, if a
design has an external buffer that reorders loads and stores for
better bus efficiency, the sync broadcast signals to that buffer
that previous loads/stores must be completed before any
following loads/stores. The sync instruction can be used to
ensure that the results of all stores into a data structure, caused
by store instructions executed in a "critical section" of a program,
are seen by other processors before the data structure is seen
as unlocked. The functions performed by the sync instruction
will normally take a significant amount of time to complete, so
indiscriminate use of this instruction may adversely affect
performance. In addition, the time required to execute sync may
vary from one execution to another. The eieio instruction may be
more appropriate than sync for many cases.
POWERPC ARCHITECTURE
LEVEL
UISA
MPC823e REFERENCE MANUAL
8
9
10
11
12
00000
24
25
26
27
28
598
SUPERVISOR
OPTIONAL
LEVEL
13
14
15
29
30
31
0
FORM
X
MOTOROLA
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