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subfze
Assembler Syntax
BIT
0
1
2
FIELD
31
BIT
16
17
18
FIELD
00000
Definition
Operation
Description
MOTOROLA
subfze
rD,rA (OE = 0 Rc = 0)
subfze.
rD,rA (OE = 0 Rc = 1)
subfzeo
rD,rA (OE = 1 Rc = 0)
subfzeo.
rD,rA (OE = 1 Rc = 1)
3
4
5
6
7
19
20
21
22
23
OE
Subtract from Zero Extended
rD ← ¬ (rA) + XER[CA]
The sum ¬ (rA) + XER[CA] is placed into rD.
Other registers altered:
Condition Register (CR0 field):
Affected: LT, GT, EQ, SO (if Rc = 1)
The CR0 field may not reflect the "true" (infinitely precise)
result if overflow occurs (see XER below).
XER:
Affected: CA
Affected: SO, OV (if OE = 1)
POWERPC ARCHITECTURE
LEVEL
UISA
MPC823e REFERENCE MANUAL
MPC823e Instruction Set—subfze
8
9
10
11
12
D
24
25
26
27
28
200
SUPERVISOR
OPTIONAL
LEVEL
13
14
15
A
29
30
31
RC
FORM
XO
B-151
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