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MB90335 Series
15.2.3
PPG0 to PPG3 Output Control Register (PPG01/PPG23)
Configuration and functions of PPG0 to PPG3 output control register (PPG01/PPG23)
are described.
■ PPG0 to PPG3 Output Control Register (PPG01/PPG23)
Figure 15.2-4 shows the bit configuration of the PPG0 to PPG3 output control registers (PPG01/PPG23).
Figure 15.2-4 PPG0 to PPG3 Output Control Register (PPG01/PPG23)
ch.0, 1 : 00004C
ch.2, 3 : 00004E
R/W : Readable/Writable
X :
Undefined value
It explains the function of each bit of the PPG0 to PPG3 output control register (PPG01/PPG23) as follows.
[bit7 to bit5] PCS2 to PCS0: ppg Count Select (count clock selection)
Selects the operation clock of the ch.1 and ch.3 down counters.
PCS2
0
0
0
0
1
1
• These bits are initialized to "000
• Reading and writing are allowed.
Note:
Since the PPG of ch.1 and ch.3 operates by receiving the count clock from the ch.0 and ch.2 in the
8-bit prescaler + 8-bit PPG mode and the 16-bit PPG mode, the specified PCS2 to PCS0 bits
become invalid.
CM44-10137-6E
bit
7
6
5
4
H
PCS2 PCS1 PCS0
PCM2
H
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
(0)
(0)
(0)
(0)
PCS1
PCS0
0
0
Peripheral Clock (41.6 ns machine clock 24 MHz time)
0
1
Peripheral Clock /2 (83.3 ns machine clock 24 MHz time)
1
0
Peripheral Clock /4 (167 ns machine clock 24 MHz time)
1
1
Peripheral Clock /8 (333 ns machine clock 24 MHz time)
0
0
Peripheral Clock /16 (667 ns machine clock 24 MHz time)
Input clock from time-base counter
1
1
9
× 167 ns=85 μs original oscillation 6 MHz time)
(2
" at reset.
B
FUJITSU MICROELECTRONICS LIMITED
15.2 Registers of 8/16-bit PPG Timer
3
2
1
0
PCM1
PCM0
Reserved
Reserved
(0)
(X)
(X)
(0)
Operating mode
CHAPTER 15 8/16-BIT PPG TIMER
PPG01/PPG23
PPG Output control register
Read/Write
Initial value
349
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