Divide Ratio Control Register (Divr0 To Divr2) - Fujitsu F2MC-16LX Hardware Manual

14.2.3 Divide Ratio Control Register (DIVR0 to DIVR2)

This section describes the configuration and functions of the divide ratio control
register (DIVR0 to 2).
I Divide ratio control register (DIVR0 to DIVR2)
Figure 14.2-4 "Bit configuration of the divide ratio control register (DIVR0 to DIVR2)" shows the
bit configuration of the divide ratio control register (DIVR0 to DIVR2).
Figure 14.2-4 Bit configuration of the divide ratio control register (DIVR0 to DIVR2)
000082
H
000084
H
000086
H
(-)
(X)
This register is only used in divide interval measurement mode (PWCSR: bits 2, 1, 0:MOD2,
MOD1, MOD0 = 001); it is not used in other modes.
In divide interval measurement mode, pulses input to the measurement pin are divided
according to the divide ratio set in this register. This allows measuring the interval width.
Table 14.2-7 Selection of divide ratio
DIV1
0
0
1
1
• Initialized to 00
• Reading and writing are allowed.
Note:
Rewriting after timer start is prohibited. Write always either before the timer is started or after
it is stopped.
7 6 5 4
- - - -
(-) (-) (-)
(X) (X) (X)
DIV0
0 Divide-by-4 [initial value]
1 Divide-by-16
0 Divide-by-64
1 Divide-by-256
at reset
B
3 2 1 0
- - DIV1 DIV0
(-) (-) (R/W) (R/W)
(X) (X) (0) (0)
Count clock selection
CHAPTER 14 PWC TIMER
DIVR
Divide ratio control register
Reading/writing
Initial value
283