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17.3.1
Address detection control register (PACSR)
The address detection control register (PACSR) enables or disables output of an
interrupt at an address match.When an address match is detected when output of an
interrupt at an address match is enabled, the INT9 interrupt is generated.
I Address detection control register (PACSR)
7
6
5
R/W
R/W
R/W
R/W
: Read / Write
: Reset value
Figure 17.3-2 Address detection control register (PACSR)
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
bit0
Reserved
bit1
AD0E
bit2
Reserved
bit3
bit4
Reserved
bit5
Reserved
bit6
Reserved
bit7
Reserved
CHAPTER 17 Address Match Detecting Function
Reset value
0 0 0 0 0 0 0 0
B
Reserved bit
Always set this bit to 0.
0
Address match detection enable bit 0
Disables the address match PADR0
0
1
Enables the address match PADR0
Reserved bit
0
Always set this bit to 0.
Address match detection enable bit 1
AD1E
0
Disables the address match PADR1
1
Enables the address match PADR1
Reserved bit
0
Always set this bit to 0.
Reserved bit
0
Always set this bit to 0.
Reserved bit
0
Always set this bit to 0.
Reserved bit
0
Always set this bit to 0.
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