Stop Mode - Fujitsu F2MC-8L Series Hardware Manual

CHAPTER 3 CPU
3.7.3

Stop Mode

This section describes the operations of stop mode.
Operation of Stop Mode
Changing to stop mode
Stop mode stops the source oscillation. Most CPU and peripheral
maintaining all register and RAM contents at their values immediately before changing to stop
mode.
In main clock mode, the subclock keeps on oscillating while the main clock stops oscillation.
Although the watch prescaler operates for incrementing and some subclock-based functions
work, therefore, the other peripheral functions and CPU stop operation, except the external
interrupt circuit.
In subclock mode, both of the main clock and subclock stop oscillation and all the functions
excluding the external interrupt circuit stop operation. Accordingly, data can be held with
minimum power consumption.
Writing "1" to the stop bit in the standby control register (STBC: STP) changes the CPU to stop
mode. At this time, external pin states are held if the pin state specification bit (STBC: SPL) is
"0". If SPL is "1", external pins go to the high-impedance state. (Pins with a pull-up resistor
(optional) go to the "H" level.)
If an interrupt request is generated when "1" is written to the STP bit, the write to the bit is
ignored, and the CPU continues the instruction execution without change to stop mode. (The
CPU does not shift to stop mode even after completion of the interrupt processing.)
In the main clock mode, prohibit interrupt request output from the timebase timer (TBTC: TBIE =
"0") before changing to stop mode as necessary. Similarly, in the subclock mode, disable watch
interrupt request output from the watch prescaler (WPCR : WIE = 0) before changing to stop
mode.
Wake-up from stop mode
A reset or an external interrupt wakes up CPU from stop mode.
If a reset occurs during stop mode on a product with power-on reset, the reset operation starts
after the oscillation stabilization delay time for the main clock.
Products without power-on reset do not require for the oscillation stabilization delay time after
triggering a reset in stop mode. The reset initializes pin states.
If an interrupt request with an interrupt level higher than "11" occurs from an external interrupt
circuit during stop mode, the CPU wakes up from stop mode, regardless of the interrupt enable
flag (CCR: I) and interrupt level bits (CCR: IL1, IL0) in the CPU. Only external interrupt requests
can occur during stop mode because peripheral functions are stopped. In main-stop mode, no
watch interrupt is generated while the watch prescaler operates.
After wake-up from stop mode, the normal interrupt operation is performed after the oscillation
stabilization delay time has passed. If the interrupt request is accepted, the CPU executes
interrupt processing. If the interrupt request is not accepted, the CPU continues execution from
the subsequent instruction following the instruction executed immediately before entering stop
mode.
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functions stop while