Stop Mode - Fujitsu MB90420/5 (A) Series Hardware Manual

5.5.4 Stop Mode

Stop mode stops the original oscillation and all functions are stopped.
lowest power consumption.
n Transition to stop mode
A transition is performed to the stop mode when 1 is written to the STP bit of the low-power consumption
mode control register (LPMCR).
• Data hold function
In the stop mode, the data in the dedicated registers such as accumulator and the internal RAM are stored.
• Operation during interrupts request issuance
During interrupt request issuance, writing 1 to STP of the low-power consumption mode control register
(LPMCR) does not transit the mode to the stop mode.
• Pin state
The SPL bit of the low-power consumption mode control register (LPMCR) controls whether to set the
external pin to the immediately preceding state or the high impedance state in the stop mode.
n Clearing stop mode
The low-power consumption controller cancels the stop mode at a reset input or a generation of interrupt. At
returning from the stop mode, the oscillation of the operating clock is stopped, so the low-power consumption
controller transits to the oscillation stabilization wait state first and then cancels the stop mode.
• Return by a reset
When the stop mode is cancelled by a reset factor, the stop mode is cancelled and then the oscillation
stabilization wait reset state occurs. The reset sequence is executed after the oscillation stabilization wait
time has elapsed.
• Return by an interrupt
When an interrupt request higher interrupt level than 7 is issued from a resource during the stop mode (the
interrupt control register ICR: IL2, IL1, IL0 = except for 111
the stop mode. After the cancellation of stop mode, interrupts are handled as normal interrupts after the
elapse of the oscillation stabilization wait time of the main clock specified by the WS1 and WS0 of the clock
select register (CKSCR). Interrupt handling is performed when an interrupt is accepted by setting of the l
flag of the condition code register (CCR), the interrupt level mask register (ILM) and the interrupt control
register (ICR). When the CPU is not ready to accept an interrupt, it executes the interrupt processing from
the instruction next to the one specifying.
Note: At the interrupt handling, the CPU usually proceeds to the interrupt handling after executing the
instruction next to the one specifying the stop mode.
concurrent with acceptance of the external bus hold request, the CPU may proceed to the interrupt
handling before executing the next instruction.
LOW-POWER CONSUMPTION MODE
5-17
Consequently, data is kept at the
), low-power consumption controller cancels
B
When a transition to the stop mode is