Asynchronous (Start-Stop Synchronization) Mode - Fujitsu FR60 Hardware Manual

CHAPTER 13 UART

13.3.1 Asynchronous (Start-stop Synchronization) Mode

When the UART is used in operating mode 0 (normal mode) or operating mode 1
(multiprocessor mode), the asynchronous transfer method is used.
■ Transfer Data Format
UART handles only data in the NRZ (Non Return to Zero) format.
Figure 13.3-1 shows the data format.
SI,SO
As shown in Figure 13.3-1, the transfer of data always starts with the start bit ("L" level data),
transfers the data bit length specified in LSB first, and ends with a stop bit ("H" level data). If an
external clock is selected, always input a clock.
The data length can be set to 7 bits or 8 bits in normal mode (Mode 0), but must be set to 8 bits
in multiprocessor mode (Mode 1). In multiprocessor mode, no parity can be added; instead, the A/
D bit is always added.
■ Receive Operation
If the RXE bit (bit1) of the SCR register is set to "1", a receive operation is always in progress.
If a start bit appears on the receive line, one-frame data is received according to the data format
specified in the SCR register. If an error occurs after reception of one frame is completed, the
error flag is set and then the RDRF flag (bit4 of the SSR register) is set. If, at this time, the RIE
bit (bit1) of the same SSR register is set to "1", a receive interrupt is generated for the CPU.
Check the flags of the SSR register and read the SIDR register if normal reception has occurred
or perform the necessary processing if an error has occurred.
The RDRF flag is cleared when the SIDR register is read.
■ Send Operation
If the TDRE flag (bit3) of the SSR register is set to "1", send data is written to the SODR
register. If, at this time, the TXE bit (bit0) of the SCR register is set to "1", transmission occurs.
The TDRE flag is set again when the data set in the SODR register is loaded into the send shift
register and begins to be transferred, indicating that the next send data can be set. If, at this
time, the TIE bit (bit0) of the same SSR register is set to "1", a send interrupt requesting that the
send data be set in the SODR register is generated for the CPU.
The TDRE flag is cleared if data is set in the SODR register.
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Figure 13.3-1 Transfer Data Format (Modes 0 and 1)
0 1 0 1 1
Start LSB
Data that has been transferred is 01001101
0 0 1 0 1 1
MSB Stop
A/D Stop
.
B
(Mode 0)
(Mode 1)