Time-Base Timer Mode - Fujitsu MB90420/5 (A) Series Hardware Manual

MB90420/5 (A) SERIES F

5.5.2 Time-base Timer Mode

Time-base timer mode stops operations other than the original oscillation, the time-base timer and the watch
timer and all functions other than the time-base timer and the watch timer are stopped.
n Transition to time-base timer mode
A transition is performed to the time-base timer mode when 0 is written to the TMD bit of the low-power
consumption mode control register (LPMCR) when the PLL clock mode or the main clock mode (CKSCR:
SCS = 1).
• Data hold function
In the time-base timer mode, data in the dedicated registers such as an accumulator and internal RAM are
stored.
• Hold function
In the time-base timer mode, the external bus hold function stops, so a hold request is not accepted even if
it is input. When a hold request is input during a transition to the time-base timer mode, the HAK signal
may not become Low with the bus in the high impedance state.
• Operation during interrupts request issuance
During interrupt request issuance, writing 0 to TMD bit of the low-power consumption mode control register
(LPMCR) does not transit the mode to the time-base timer mode.
• Pin state
The SPL bit of the low-power consumption mode control register (LPMCR) controls whether to set the
external pin to the immediately preceding state or to the high impedance state in the time-base timer
mode.
n Cancellation of time-base timer mode
The low-power consumption controller cancels the time-base timer mode at a reset input or a generation of
interrupt issuance.
• Return by a reset
At a reset, time-base timer is initialized to the main clock mode.
• Return by an interrupt
When interrupt request with a higher level than 7 is issued from a resource dueing the time-base timer
mode, (the interrupt control register ICR: IL2, IL1 and IL0 = except for 111
controller cancels the time-base timer mode. After the time-base timer is cleared, interrupts are handled
as normal interrupts. Interrupt handling is performed when an interrupt is accepted by the setting of the I
flag of the condition code register (CCR), the interrupt level mask register (ILM) and the interrupt control
register (ICR). When the CPU is not ready to accept an interrupt, it executes the interrupt handling from
the instruction next to the one specifying.
Note: At interrupt handling, the CPU usually proceeds to the interrupt handling after executing the
instruction next to the one specifying the time-base timer mode. When a transition to the time-base
timer mode is concurrent with acceptance of the external bus hold request, the CPU may proceed to
the interrupt handling before executing the next instruction.
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MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL
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), the low-power consumption
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