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12.6.4.8
Transmit Short Packet (TSP)
The software uses the transmit short packet bit to indicate that the last byte of a data transfer to the
FIFO has occurred. This indicates to the UDC that a short packet or zero-sized packet is ready to
transmit. Software must not set this bit if a 64-byte packet is to be transmitted. When the data
packet is successful transmitted, the UDC clears this bit.
These are read/write registers. Ignore reads from reserved bits. Write zeros to reserved bits.
12.6.5
UDC Endpoint x Control/Status Register (UDCCS2/7/12)
UDCCS2/7/12, shown in
OUT endpoint.
Table 12-16. UDCCS2/7/12 Bit Definitions
0x 4060_0018
0x 4060_002C
0x 4060_0040
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
x
x
x
x
x
x
Bit
Name
31:8
7
RSP
6
RNE
5
4
3
DME
2
1
RPC
0
Intel® PXA255 Processor Developer's Manual
Table
12-16, contains 7 bits that are used to operate endpoint x, a Bulk
reserved
x
x
x
x
x
x
x
—
reserved
Receive short packet (read-only).
1 = Short packet received and ready for reading.
Receive FIFO not empty (read-only).
0 = Receive FIFO empty.
1 = Receive FIFO not empty.
Force stall (read/write).
FST
1 = Issue STALL handshakes to OUT tokens.
Sent stall (read/write 1 to clear).
SST
1 = STALL handshake was sent.
DMA Enable(read/write)
0 = Send data received interrupt after EOP received
1 = Send data received interrupt after EOP received and Receive FIFO has < 32 bytes of
data
—
reserved
Receive packet complete (read/write 1 to clear).
0 = Error/status bits invalid.
1 = Receive packet has been received and error/status bits are valid.
Receive FIFO service (read-only).
RFS
0 = Receive FIFO has less than 1 data packet.
1 = Receive FIFO has 1 or more data packets.
UDCCS2
UDCCS7
UDCCS12
x
x
x
x
x
x
x
x
Description
USB Device Controller
USB Device Controller
8
7
6
5
4
3
x
x
x
0
0
0
0
0
2
1
0
0
0
0
12-29
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