Gedr0 Bit Definitions; Gedr1 Bit Definitions - Intel PXA255 Developer's Manual

4.1.3.5 GPIO Edge Detect Status Register (GEDR0, GEDR1, GEDR2)
GEDR0, GEDR1, GEDR2, shown in
status bits that correspond to the 85 GPIO pins. When an edge detect occurs on a pin that matches
the type of edge programmed in the GRER and/or GFER registers, the corresponding status bit is
set in GEDR. Once a GEDR bit is set by an edge event, the bit remains set until the user clears it by
writing a one to the status bit. Writing a zero to a GEDR status bit has no effect.
Each edge detect that sets the corresponding GEDR status bit for GPIO[84:0] can trigger an
interrupt request. GPIO[84:2] together form a group that can cause one interrupt request to be
triggered when any one of GEDR[84:2] are set. GPIO[0] and GPIO[1] cause independent first-
level interrupts. Refer to
Table 4-21
Table 4-21. GEDR0 Bit Definitions
Physical Address
0x40E0_0048
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
Reset 0 0 0 0 0 0
Bits Name
<31:0> ED[x]
Table 4-22. GEDR1 Bit Definitions
Physical Address
0x40E0_004C
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
Reset 0 0 0 0 0 0
Bits Name
<31:0> ED[x]
Intel® PXA255 Processor Developer's Manual
Section 4.2, for a description of the programming of GPIO interrupts.
through Table 4-23 show the bitmaps of the GEDR0, GEDR1, and GEDR2.
0 0 0 0 0 0 0 0
GPIO Pin 'x' Edge Detect Status (where x= 0 through 31).
READ
0 – No edge detect has occurred on pin as specified in GRER and/or GFER.
1 – Edge detect has occurred on pin as specified in GRER and/or GFER.
WRITE
0 – No effect.
1 – Clear edge detect status field.
0 0 0 0 0 0 0 0
GPIO Pin 'x' Edge Detect Status (where x= 32 through 63).
READ
0 – No edge detect has occurred on pin as specified in GRER and/or GFER.
1 – Edge detect has occurred on pin as specified in GRER and/or GFER.
WRITE
0 – No effect.
1 – Clear edge detect status field.
Table 4-21, Table 4-22, and
GEDR0
0 0 0 0 0 0 0 0
Description
GEDR1
0 0 0 0 0 0 0 0
Description
System Integration Unit
Table 4-23, contain a total of 85
System Integration Unit
8 7 6 5 4 3 2
0 0 0 0 0 0 0 0
System Integration Unit
8 7 6 5 4 3 2
0 0 0 0 0 0 0 0
1 0
0 0
1 0
0 0
4-15