14Additional Power Sequencing Considerations; 15Power Sequence Timing Diagram; Power Sequence Timing - Intel Quark SoC X1000 Design Manual

15.3.14 Additional Power Sequencing Considerations
It is possible that on rare occasions, wake events can cause the system to immediately
wake after entering in S3 power state. In such circumstances it is possible that the SoC
will generate the same duration pulse widths on the v3p3_s0_en, v1p5_s0_en and
v1p0_s0_en as during normal cold boot. Care should be taken during the platform
design to evaluate and account for such events in terms of VR design, power good
circuitry design, and overall platform power sequencing in order to ensure timing
specifications related to power sequencing are not violated.
15.3.15 Power Sequence Timing Diagram
Figure 50.

Power Sequence Timing

VCC3P3_S5
VCC1P5_S5
VCC1V8_S5
VCC1V0_S5
SLDO power good(internal)
platform_S5_pwrok
(VCC3P3_S5 @ 90%)
negedge_pwr_btn/ auto start
S3_3V3_EN
S3_1V5_EN
VCC3P3_S3
VCC1P8_S3
VCC1P0_S3
VCC1P5_S3
platform_s3_pwrok
(VCC3P3_S3 @ 90%)
S0_3V3_EN
S0_1V5_EN
VCC3P3_S0
VCC1P8_S0
VCC1P5_S0
platform_s0_pwrok
(VCC3P3_S0 @ 90%)
S0_1V0_EN
VCC1P0_S0
platform_1P0_s0_pwrok
(VCC1P0_S0 @ 90%)
®
Intel Quark™ SoC X1000
PDG
104
SLDO Ramp Time
At 75%
PLL lock time
®
Intel Quark™ SoC X1000—Platform Reset Considerations
FET Ramp Time
SLDO Ramp Time
FET Ramp Time
nd
2 PLL Lock
FET Ramp Time
SLDO Ramp Time
FET Ramp Time
§ §
FET Ramp Time
June 2014
Order Number: 330258-002US