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Intel Pentium M Processor Design Manual

Intel Pentium M Processor Design Manual

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®
®
Intel
Pentium
M Processor and
®
the Intel
E7501 Chipset Platform
®
®
®
For use with the Intel
Pentium
M Processor and the Intel
®
Pentium
M Processor on the 90 nm process with 2-MB L2 cache
Design Guide
January 2007
Order Number: 273871-007

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  • Page 1 M Processor and ® the Intel E7501 Chipset Platform ® ® ® For use with the Intel Pentium M Processor and the Intel ® Pentium M Processor on the 90 nm process with 2-MB L2 cache Design Guide January 2007...
  • Page 2 Intel products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications. Intel may make changes to specifications and product descriptions at any time, without notice.

  • Page 3: Table Of Contents

    E7501 Chipset ..................... 27 ® 1.3.3.1 Intel E7501 Memory Controller Hub (MCH) ......... 27 ® 1.3.3.2 I/O Controller Hub 3 (Intel 82801CA ICH3-S) Features....... 28 ® 1.3.3.3 PCI/PCI-X 64-bit Hub 2 (Intel P64H2) Features ........28 1.3.4 Peak Bandwidth Summary ..................29 1.3.5...
  • Page 4 ® ® ® Intel Pentium M Processor and Intel E7501 Chipset Platform Contents 5.1.3 Recommended Stack-up Routing and Spacing Assumptions ....... 59 5.1.4 Trace Space to Trace - Reference Plane Separation Ratio ........59 5.1.4.1 Trace Space to Trace Width Ratio............59 5.1.4.2...
  • Page 5 Hub Interface 1.5 Resistive Compensation............122 7.3.4 Hub Interface 1.5 Decoupling Guidelines ............122 ® Intel 82870P2 (Intel P64H2) ..................... 123 PCI/PCI-X Design Guidelines ................... 123 8.1.1 General PCI-X Routing Guidelines ..............124 8.1.2 PCI/PCI-X Routing Requirements (No Hot-Plug Switch) ........125 8.1.3...
  • Page 6 ® 8.2.10 Intel P64H2 PCI Interface PCIXCAP and M66EN Pins ........148 8.2.10.1 PCIXCAP Pin Requirements..............148 8.2.10.2 M66EN Pin Requirements ..............149 ® I/O Controller Hub 3 (Intel ICH3-S)..................153 IDE Interface........................153 9.1.1 Cabling......................... 153 9.1.2 Cable Detection for Ultra ATA/66 and Ultra ATA/100.......... 153 9.1.2.1...
  • Page 7 9.7.4 Critical Dimensions ....................176 9.7.4.1 Distance from Magnetics Module to RJ45 (Distance A) ...... 177 9.7.4.2 Distance from Intel® 82562ET to Magnetics Module (Distance B) ..177 9.7.5 Terminating Unused Connections ...............177 9.7.5.1 Termination Plane Capacitance ............178 Debug Port and Logic Analyzer Interface ................179 10.1...
  • Page 8 E7501 Chipset Platform Contents 11.3 Processor Power Delivery Design Guidelines ..............192 11.3.1 Processor PLL Power Delivery ................192 ® ® 11.3.2 Voltage Identification for Intel Pentium M Processor........192 11.3.3 V Power Sequencing ................194 CC_CORE 11.3.4 VCCP Output Requirements................194 11.3.5 Thermal Power Dissipation..................
  • Page 9 13.2 MCH Schematic Checklist ....................248 ® 13.3 Intel ICH3-S Schematic Checklist...................252 ® 13.4 Intel 82870P2 (Intel P64H2) Schematic Checklist ............260 13.5 CK408 Schematic Checklist ..................... 265 Layout Checklist ........................267 14.1 Processor Checklist ......................267 ® 14.2 Intel E7501 MCH Layout Checklist .................
  • Page 10 ® ® ® Intel Pentium M Processor and Intel E7501 Chipset Platform Contents Figures ® ® ® Intel Pentium M Processor and Intel E7501Chipset-Based System Configuration Example ....................... 30 ® ® Intel Pentium M Processor Quadrant Layout (Top View) ............32 ®...
  • Page 11 ® ® ® Intel Pentium M Processor and Intel E7501 Chipset Platform Contents 49 DDR VREF Voltage Divider ......................89 50 Dual Channel Routing DDRVREF and ODTCOMP..............89 51 Dual Channel DDRCVO Routing Guidelines ................90 52 DDR VTerm Plane ........................91 53 1-DIMM Per Channel Decoupling ....................92 54 2-DIMMs Per Channel Decoupling .....................
  • Page 12 ® ® ® Intel Pentium M Processor and Intel E7501 Chipset Platform Contents 99 Reference Schematic for Single-Slot Parallel Mode..............141 100 Dual-Slot Parallel SMBus Circuit ....................144 101 Reference Schematic for Dual-Slot Parallel Mode ..............145 102 Four-Slot Stutter Logic Implementation Example ..............147 103 Reference Schematic for Serial Mode ..................
  • Page 13 ® ® ® Intel Pentium M Processor and Intel E7501 Chipset Platform Contents 149 Serpentine Spacing-Spacing to Reference Plane Height Ratio..........217 150 Spread Spectrum Modulation Profile ..................219 151 Impact of Spread Spectrum Clocking on Radiated Emissions ..........220 152 Cancellation of H-fields Through Inverse Currents ..............220 153 Length Tuning Parameters .......................
  • Page 14 ® ® ® Intel Pentium M Processor and Intel E7501 Chipset Platform Contents Tables Reference Documents ........................ 19 Conventions and Terminology ....................21 ® ® ® Intel Pentium M Processor or Intel E7501 Chipset Platform Peak Bandwidth Summary..29 Board Requirements........................38 CK408 Clock Groups ........................
  • Page 15 ® ® ® Intel Pentium M Processor and Intel E7501 Chipset Platform Contents 45 Single Channel Source Clocked Signal Group Routing Guidelines.......... 101 46 Single Channel Chip Select Routing Guidelines...............102 47 Single Channel Clock Enable Routing Guidelines..............103 48 Single Channel Receive Enable Routing Guidelines ..............104 49 DDRCOMP Routing Guidelines....................
  • Page 16 ® ® ® Intel Pentium M Processor and Intel E7501 Chipset Platform Contents 95 Processor Schematic Checklist ....................243 96 MCH Schematic Checklist ......................248 ® 97 Intel ICH3-S Schematic Checklist................... 252 ® 98 Intel P64H2 Schematic Checklist ................... 260 99 CK408 Schematic Checklist .....................
  • Page 17 August 2004 Added support for Intel Pentium M Low Voltage 738 Processor. ® ® Added support for the Intel Pentium M Processor on the 90 nm process with 2-MB L2 cache June 2004 Updated recommendation for TEST[1] pin. Changes to the command clock and chip select routing in the Memory July 2003 Interface Guidelines chapter.
  • Page 18 ® ® ® Intel Pentium M Processor and Intel E7501 Chipset Platform Contents Design Guide...

  • Page 19: Introduction

    ® Intel E7501 Chipset-based systems. Recommendations are subject to change. Board designers may use the associated Intel schematics as a reference. While the schematics cover ® ® a specific design implementation, the core schematics remain the same for most Intel Pentium ®...
  • Page 20 M Processor on the 90 nm Process with 2-MB L2 Cache http://developer.intel.com/design/mobile/ Datasheet datashts/302189.htm ® ® Intel Pentium M Processor on the 90 nm Process with 2-MB L2 Cache http://developer.intel.com/design/mobile/ Specification Update specupdt/302209.htm Note: Contact your Intel Field Representative for additional reference documentation. Design Guide...

  • Page 21: Terminology

    ® ® ® Intel Pentium M Processor and Intel E7501 Chipset Platform Introduction Terminology This section defines terminology used throughout the design guide. Table 2. Conventions and Terminology (Sheet 1 of 4) Terminology Description Aggressor A network that transmits a coupled signal to another network.
  • Page 22 ® ® ® Pentium M processor The Intel Pentium M Processor or the Intel Pentium M Processor on the 90 nm process with 2-MB L2 Cache. Both processors share a common design guide. Pin/Ball The contact point of a component package to the traces on a substrate, such as the motherboard.
  • Page 23 E7501 Memory Controller Hub contains an integrated processor and DRAM interface. ® Intel ICH3-S A component of the Intel E7501 chipset, the Intel 82801CA I/O Controller Hub 3-S contains the primary PCI interface, LPC interface, USB, ATA-100, and other legacy functions.

  • Page 24: System Overview

    A component of the Intel E7501 chipset, the Intel 82870P2 PCI / PCI-X 64-bit Hub 2 Bus Controller. Hub Interface (HI) Intel high speed proprietary hub interconnect, known as the Hub Interface (HI), ® ® that interfaces the Intel E7501 chipset to the Intel ICH3-S and Intel P64H2.

  • Page 25: Architectural Features

    SpeedStep Technology. Unlike previous implementations of Intel SpeedStep technology, this technology enables the processor to switch between multiple frequency and voltage points instead of two. This will enable superior performance with optimal power savings. Switching between states is software controlled unlike previous implementations where the GHI# pin is used to toggle between two states.

  • Page 26: Intel ® Pentium ® M Processor On The 90 Nm Process With 2-Mb L2 Cache

    — The processor waits for a fixed time period. If the die temperature is down to acceptable levels, an up transition to the previous frequency/voltage point occurs. — An interrupt is generated for the up and down Intel Thermal Monitor transitions enabling better system level thermal management.

  • Page 27: Intel ® E7501 Chipset

    The chipset components communicate through Hub Interfaces (HIs). The MCH provides four Hub Interface connections: one HI1.5 for the ICH3-S and three HI2.0s for high-speed I/O using Intel P64H2 components. The Hub Interfaces are point-to-point and therefore only support two components (the MCH plus one I/O device).

  • Page 28: I/O Controller Hub 3 (Intel 82801Ca Ich3-S) Features

    1.3.3.2 I/O Controller Hub 3 (Intel 82801CA ICH3-S) Features ® The I/O Controller Hub 3 (ICH3-S) provides the legacy I/O subsystem for Intel E7501 Chipset- based platforms. Additionally, it integrates many advanced I/O functions. The ICH3-S includes the following features: •...

  • Page 29: Peak Bandwidth Summary

    Hub Interface A Hub Interface B, C, D 1066 PCI-X 1066 1.3.5 System Configurations ® Figure 1 illustrates an example Intel E7501 Chipset-based system configuration for server or ® ® embedded platforms using the Intel Pentium M Processor. Design Guide...

  • Page 30: Configuration Example

    ® ® ® Intel Pentium M Processor and Intel E7501 Chipset Platform Introduction ® ® ® Figure 1. Intel Pentium M Processor and Intel E7501Chipset-Based System Configuration Example Processor System Memory DDR-200 DDR-200 16-bit PCI / PCI-X HI 2.0 Intel®...

  • Page 31: Component Quadrant Layout

    ® ® ® Intel Pentium M Processor and Intel E7501 Chipset Platform Component Quadrant Layout Component Quadrant Layout The following figures show only general quadrant information, not exact component pin count. Designers should use only the exact pin assignment to conduct routing analyses. Reference the following documents for exact pin assignment information.

  • Page 32: Intel ® Pentium ® M Processor Quadrant Layout

    Component Quadrant Layout ® ® Intel Pentium M Processor Quadrant Layout ® ® Figure 2 shows the top view of the Intel Pentium M Processor quadrant layout. ® ® Figure 2. Intel Pentium M Processor Quadrant Layout (Top View) Common...

  • Page 33: Intel ® E7501 Chipset Mch Quadrant Layout

    E7501 Chipset Platform Component Quadrant Layout ® Intel E7501 Chipset MCH Quadrant Layout ® Figure 3 shows the top view of the Intel E7501 Chipset MCH quadrant layout. ® Figure 3. Intel E7501 Chipset MCH Quadrant Layout (Top View) DDR A...

  • Page 34: Intel ® Ich3-S Quadrant Layout

    M Processor and Intel E7501 Chipset Platform Component Quadrant Layout ® Intel ICH3-S Quadrant Layout ® Figure 4 shows the top view of the Intel ICH3-S quadrant layout. ® Figure 4. Intel ICH3-S Quadrant Layout (Top View) Ac'97/ Interface GPIO...

  • Page 35: Intel ® P64H2 Quadrant Layout

    M Processor and Intel E7501 Chipset Platform Component Quadrant Layout ® Intel P64H2 Quadrant Layout ® Figure 5 shows the top view of the Intel P64H2 quadrant layout. ® Figure 5. Intel P64H2 Quadrant Layout (Top View) Hub Interface IRQs Hot Plug VCC3.3...
  • Page 36 ® ® ® Intel Pentium M Processor and Intel E7501 Chipset Platform Component Quadrant Layout Design Guide...

  • Page 37: Baseboard Requirements

    Table 4 when designing their boards. Intel realizes numerous ways exist to achieve these targeted impedance tolerances; contact your board vendor for these specifics. Intel encourages platform designers to perform comprehensive simulation analysis to ensure all timing specifications are met. This is particularly important when a design deviates from the design guidelines provided.

  • Page 38: Processor Thermal Solution Placement And Recommended Keep-Outs

    • Discrete 0603, 0805 back side. Processor Thermal Solution Placement and Recommended Keep-Outs ® For thermal solution mechanical keep-outs in embedded form factors please refer to the Intel ® Pentium M Processor for Embedded Applications Thermal Design Guide. Design Guide...

  • Page 39: Platform Clock Routing Guidelines

    Platform Clock Routing Guidelines Platform Clock ® To minimize jitter, improve routing, and reduce cost, Intel E7501 chipset-based systems should use a single chip clock solution, the CK408 or CK408B. The difference between the CK408 and the CK408B is the CK408B provides one additional 100 MHz differential outputs pair. The clock chip provides three (CK408) or four (CK408B) 100 MHz differential output pairs for the processor and MCH, including the ITP connector, and six 66 MHz speed clocks that drive all I/O buses.
  • Page 40 ® ® ® Intel Pentium M Processor and Intel E7501 Chipset Platform Platform Clock Routing Guidelines Table 6. Platform System Clock Reference (Sheet 2 of 2) Clock Group CK-408 Pin Component Component Pin Name 32-bit PCI Connector PCI Video Down...

  • Page 41: System Clocking Diagram Example

    ® ® ® Intel Pentium M Processor and Intel E7501 Chipset Platform Platform Clock Routing Guidelines Figure 7. System Clocking Diagram Example Processor CLK33 Design Guide...

  • Page 42: Host_Clk Clock Group

    ® ® ® Intel Pentium M Processor and Intel E7501 Chipset Platform Platform Clock Routing Guidelines HOST_CLK Clock Group The clock synthesizer provides four sets of 100 MHz differential clock outputs. For this platform three sets of 100 MHz differential clock outputs are used. The 100 MHz differential clocks are driven to the Processor, the MCH, and the processor’s debug port as shown in...

  • Page 43: Host_Clk[1:0]# Routing Guidelines

    ® ® ® Intel Pentium M Processor and Intel E7501 Chipset Platform Platform Clock Routing Guidelines Table 7. HOST_CLK[1:0]# Routing Guidelines (Sheet 1 of 2) Layout Guideline Value Reference Notes 300 ps total budget: Figure 8 HOST_CLK Skew between Agents...

  • Page 44: Clock Skew As Measured From Agent To Agent

    ® ® ® Intel Pentium M Processor and Intel E7501 Chipset Platform Platform Clock Routing Guidelines Table 7. HOST_CLK[1:0]# Routing Guidelines (Sheet 2 of 2) Layout Guideline Value Reference Notes Ω ± 5% Rs Series Termination Value Figure 8 Ω...

  • Page 45: Bclk Length Matching Requirements (Mfcpga)

    Processor shortest(L1/L1’) = MCH longest(L1/L1’) ± 10 mils. ® ® Additionally, the routing of each half of the host clock pair for the Intel Pentium M processor and MCH should be trace length matched within ± 10 mils of its complement’s routing (i.e., the following relationships should be adhered to): Processor (L1 + L2 + L4) = Processor (L1’...

  • Page 46: Ck408 Vs. Ck408B Requirement

    ® ® ® Intel Pentium M Processor and Intel E7501 Chipset Platform Platform Clock Routing Guidelines 4.2.3 CK408 vs. CK408B Requirement The CK408 and CK408B are pin compatible. The only difference between the two chips is the CK408B replaces two signals on the CK408 with a fourth HOST_CLK pair. The fourth HOST_CLK pair is connected to the debug port also known as the In Target Probe (ITP).

  • Page 47: Clk66 Clock Group

    CLK66 Clock Group In the CLK66 clock group, the driver is the clock synthesizer 66 MHz clock output buffer, and the ® receiver is the 66 MHz clock input buffer at the MCH, Intel ICH3-S, and Intel P64H2. Figure 12.

  • Page 48: Clk66 Skew Requirements

    Each connector is equivalent to 0.60 inch of trace. Adding a single connector on the Intel P64H2 trace would reduce the motherboard trace length by the card length as shown in the following equation and Figure "Z"...

  • Page 49: Example Of Adding A Single Connector

    ® ® ® Intel Pentium M Processor and Intel E7501 Chipset Platform Platform Clock Routing Guidelines Figure 14. Example of Adding a Single Connector NOTES: 1. All lengths must be matched within 100-mils of target length. 2. 66 MHz clock lines routed with 25-mils isolation from any other signal.

  • Page 50: Clk33_Ich3-S Clock Group

    ® ® ® Intel Pentium M Processor and Intel E7501 Chipset Platform Platform Clock Routing Guidelines CLK33_ICH3-S Clock Group For the CLK33_ICH3-S clock group, the driver is the clock synthesizer PCIF 33 MHz clock output buffer, and the receiver is the PCICLK 33 MHz clock input buffer at the ICH3-S. Care must be taken to length match this 33 MHz clock with the ICH3-S 66 MHz clock.

  • Page 51: Topology For Clk33 To Pci Slot

    ® ® ® Intel Pentium M Processor and Intel E7501 Chipset Platform Platform Clock Routing Guidelines Table 10. CLK33 Routing Guidelines for PCI Device Down Parameter Routing Guidelines Clock Group CLK33 Topology Point-to-Point Reference Plane Ground referenced (contiguous over entire length) 50 Ω...

  • Page 52: Clk14 Clock Group

    ® ® ® Intel Pentium M Processor and Intel E7501 Chipset Platform Platform Clock Routing Guidelines CLK14 Clock Group The driver in the CLK14 clock group is the clock synthesizer 14.318 MHz clock output buffer (pin REF0), and the receiver is the 14.318 MHz clock input buffer at the ICH3-S, SIO and LPC.

  • Page 53: Usbclk Clock Group

    ® ® ® Intel Pentium M Processor and Intel E7501 Chipset Platform Platform Clock Routing Guidelines USBCLK Clock Group For the USBCLK clock group, the driver is the clock synthesizer USB clock output buffer (pin USB-48 MHz), and the receiver is the USB clock input buffer at the ICH3-S (pin CLK48).

  • Page 54: Clock Driver Decoupling

    ® ® ® Intel Pentium M Processor and Intel E7501 Chipset Platform Platform Clock Routing Guidelines Clock Driver Decoupling The decoupling requirements for a CK408 compliant clock synthesizer are as follows: • One, 22 µF polarized (decoupling) capacitor placed close to the VDD generation circuitry.

  • Page 55: Clock Driver Power Delivery

    ® ® ® Intel Pentium M Processor and Intel E7501 Chipset Platform Platform Clock Routing Guidelines Clock Driver Power Delivery Designers must take special care to provide a quiet VDDA supply to the Ref VDD, VDDA and the 48 MHz VDD. These VDDA signals are especially sensitive to switching noise induced by the other VDDs on the clock chip.
  • Page 56 ® ® ® Intel Pentium M Processor and Intel E7501 Chipset Platform Platform Clock Routing Guidelines Design Guide...

  • Page 57: System Bus Routing Guidelines

    The most accurate way to understand the signal integrity and timing of the Intel Pentium M processor system bus in your platform is by performing a comprehensive simulation analysis.

  • Page 58: Processor System Bus Termination

    Use this as a quick reference only. The following sections provide more detailed information for each parameter. Intel strongly recommends simulation of all signals to ensure the design meets setup and hold times.

  • Page 59: Recommended Stack-Up Routing And Spacing Assumptions

    An edge-to-edge trace spacing (2X) to trace-reference plane separation (X) ratio of 2:1 ensures a low crosstalk coefficient. All of the ® effects of crosstalk are difficult to simulate. The timing and layout guidelines for the Intel ® Pentium M processor have been created with the assumption of a 2:1 trace spacing to trace- reference plane ratio.

  • Page 60: Processor Reset# Signal

    ITP700FLEX debug port is implemented, a simple point-to-point ® ® connection between the CPURESET# pin of the MCH and Intel Pentium M processor’s RESET# pin is recommended. On-die termination of the AGTL+ buffers on both the processor and the MCH provide proper signal quality for this connection.

  • Page 61: Source Synchronous Signals

    It is OK to split different groups of source synchronous signals between different motherboard layers as long as all the signals that belong to that group are kept on the same layer. Grouping of Intel Pentium M processor system bus source synchronous signals is summarized in and Table 20.

  • Page 62: Source Synchronous - Data

    For the recommended stack-up example, Figure Skew minimization requires pad-to-pad trace length matching of the Intel Pentium M processor system bus source synchronous signals that belong to the same group including the strobe signals of that group.

  • Page 63: Source Synchronous - Address

    ® ® ® Intel Pentium M Processor and Intel E7501 Chipset Platform System Bus Routing Guidelines ® ® Table 19. Intel Pentium M Processor System Bus Source Synchronous Data Signal Routing Guidelines Signal Names Total Trace Length Normal Width and...

  • Page 64: Common Clock Signals

    Although every attempt should be made to maximize the signal spacing in these areas, it is allowable to have 1:1 trace spacing underneath the MCH and the Intel Pentium M processor package outlines and up to <500 mils outside the outer ball array.

  • Page 65: Asynchronous Signals

    Therefore, it is very important to follow the recommended termination voltage for these signals. ® ® 5.1.7.1.1 Topology 1A: Open Drain (OD) Signals Driven by the Intel Pentium M Processor – IERR# The Topology 1A OD signal IERR# should adhere to the following routing and layout recommendations.

  • Page 66: Routing Illustration For Topology 1A

    V (1.05 V). It is recommended that the FERR# signal of the Intel Pentium M processor be routed to the FERR# signal of the Intel ICH3-S. THERMTRIP# may be implemented in a number of ways to meet design goals.

  • Page 67: Routing Illustration For Topology 1C

    Table 25 lists the recommended routing requirements for the PROCHOT# signal of the Intel Pentium M processor. The routing guidelines allows the signal to be routed as either a micro-strip or strip-line using 50 Ω ± 10% characteristic trace impedance.

  • Page 68: Routing Illustration For Topology 2A

    (1.05 V). Note that the Intel ICH3-S CPUPWRGD signal should be routed point-to-point to the Intel Pentium M processor’s PWRGOOD signal. The routing from the Intel Pentium M processor’s PWRGOOD pin should fork out to both the termination resistor, R and the ICH3-S. Segments L1 and L2 from...

  • Page 69: Voltage Translation Logic

    ® ® ® Intel Pentium M Processor and Intel E7501 Chipset Platform System Bus Routing Guidelines Series resistor R is a component of the voltage translator logic circuit and serves as a driver isolation resistor. R is shown separated by distance L3 from the first bipolar junction transistor (BJT), Q1, to emphasize the placement of Rs with respect to Q1.

  • Page 70: Agtl+ I/O Buffer Compensation

    M processor, the COMP[2] and COMP[0] pins must each be pulled-down to ground with 27.4 Ω ± 1% resistors and should be connected to the Intel Pentium M processor with a trace impedance of 27.4 Ω. The resistor must be less than 0.5 inches from the processor pins.

  • Page 71: Intel ® Pentium ® M Processor System Bus Strapping

    M processor has pins that require termination for proper component operation. 1. For the Intel Pentium M processor, a stuffing option should be provided for the TEST[3:1] pins to allow a 1 kΩ ± 5% pull-down to ground for testing purposes. For proper processor operation with the E7501 chipset, only the TEST[1] pin resistor should be stuffed, while the TEST [3:2] resistors should remain unstuffed.

  • Page 72: Design Recommendations

    ® ® ® Intel Pentium M Processor and Intel E7501 Chipset Platform System Bus Routing Guidelines ® ® 5.1.10 Intel Pentium M Processor V CCSENSE SSSENSE Design Recommendations ® ® The V and V signals of the Intel Pentium M processor provide isolated, low...

  • Page 73: Memory Interface Routing Guidelines

    Each DDR interface has six signal types: Command Clocks, Source Clocked Signals, Source ® Synchronous Signals, Chip Selects, Clock Enable, and DC Biasing. Refer to the Intel E7501 Chipset Memory Controller Hub (MCH) Datasheet for details on the signals.

  • Page 74: Ddr Channel Impedance Requirements

    ® ® ® Intel Pentium M Processor and Intel E7501 Chipset Platform Memory Interface Routing Guidelines Table 30. DDR Channel Signal Groups (Sheet 2 of 2) Group Signal DQS_x[17:0] Source Synchronous Signals DQ_x[63:0] CB_x[7:0] CMDCLK_x[3:0] Command Clocks CMDCLK_x[3:0]# Chip Selects...

  • Page 75: Dimm Types

    ® ® ® Intel Pentium M Processor and Intel E7501 Chipset Platform Memory Interface Routing Guidelines Figure 34. Trace Width and Spacing for All DDR Signals Except CMDCLK_x[3:0]/ CMDCLK_x[3:0]# Layer 1 Signal 2.1 mil (1 oz + plating) Dielectric Dielectric 3.8 mil...

  • Page 76: Dual Channel Ddr Overview

    DIMM ordering, SMBus Addressing, Command Clock routing and Chip Select routing documented in Figure 36 Figure 37. This addressing must be maintained to be compliant with the reference BIOS code supplied by Intel. Design Guide...
  • Page 77 DIMMs furthest from the MCH when a combination of single-ranked and double-ranked DIMMs is used (see Figure 38). To determine if a registered DDR DIMM is a single-bank DIMM or a double-bank DIMM, contact your local Intel representative for more information. Design Guide...

  • Page 78: Dual Channel Source Synchronous Signal Group Routing

    ® ® ® Intel Pentium M Processor and Intel E7501 Chipset Platform Memory Interface Routing Guidelines Figure 38. Example of Proper Single and Dual Rank Mixing Figure 39. Example of Incorrect Single and Dual Rank Mixing 6.3.1 Dual Channel Source Synchronous Signal Group Routing The MCH source synchronous signals are divided into groups consisting of data bits (DQ) and check bits (CB).
  • Page 79 ® ® ® Intel Pentium M Processor and Intel E7501 Chipset Platform Memory Interface Routing Guidelines Table 32. DQ/CB to DQS Mapping (Sheet 2 of 2) † Data Group Associated Strobe DQ_x[55:48] DQS6, DQS15 DQ_x[63:56] DQS7, DQS16 CB_x[7:0] DQS8, DQS17 †...

  • Page 80: Dual Channel Source Synchronous Signal Group Routing Guidelines

    E7501 MCH package trace lengths. 3. Route all data signals and their associated strobes on the same layer from MCH to Rtt. 4. The MCH to DIMM1 trace length is defined as Intel E7501 MCH die pad (PCB trace velocity equivalent, see Section 12.6, “Length...

  • Page 81: Dual Channel Source Synchronous Topology Dimm Solution

    ® ® ® Intel Pentium M Processor and Intel E7501 Chipset Platform Memory Interface Routing Guidelines Figure 40. Dual Channel Source Synchronous Topology DIMM Solution DDR VTERM (1.25V) DQ/CB Data Group Channel A Associated DQS DQ/CB Data Group Channel B...

  • Page 82: Dual Channel Command Clock Routing

    ® ® ® Intel Pentium M Processor and Intel E7501 Chipset Platform Memory Interface Routing Guidelines 6.3.2 Dual Channel Command Clock Routing Only one differential clock pair is routed to each DIMM connector because the MCH only supports registered DDR DIMMs. All CMDCLK/CMDCLK# termination is on the DIMM modules. Route each clock and its compliment adjacent to each other.

  • Page 83: Dual Channel Source Clocked Signal Group Routing

    ® ® ® Intel Pentium M Processor and Intel E7501 Chipset Platform Memory Interface Routing Guidelines Figure 42. Dual Channel 2-DIMM Command Clock Topology A_CMDCLK0 & CMDCLK0# Channel A A_CMDCLK1 & CMDCLK1# B_CMDCLK0 & CMDCLK0# Channel B B_CMDCLK1 & CMDCLK1#...

  • Page 84: Dual Channel Chip Select Routing

    ® ® ® Intel Pentium M Processor and Intel E7501 Chipset Platform Memory Interface Routing Guidelines Figure 43. Dual Channel Source Clocked Signal Topology DDR VTERM (1.25V) RAS#, CAS#, WE# Channel A MA[12:0], BA[1:0] RAS#, CAS#, WE# Channel B MA[12:0], BA[1:0]...

  • Page 85: Dual Channel Clock Enable Routing

    ® ® ® Intel Pentium M Processor and Intel E7501 Chipset Platform Memory Interface Routing Guidelines Table 36. Dual Channel Chip Select Routing Guidelines (Sheet 2 of 2) 1-DIMM 2-DIMM 2-DIMM 3-DIMM 4-DIMM Solution Parameter Solution Solution Solution Solution Reference 90°...

  • Page 86: Dual Channel Dc Biasing Signals

    ® ® ® Intel Pentium M Processor and Intel E7501 Chipset Platform Memory Interface Routing Guidelines Table 37. Dual Channel Clock Enable Routing Guidelines 1-DIMM 2-DIMM 2-DIMM 3-DIMM 4-DIMM Parameter Solution Solution Solution Solution Solution Reference 0°, 25°, 90° 25°...

  • Page 87: Dual Channel Receive Enable Signal (Rcven#)

    The MCH uses DDRCOMP_x to calibrate the DDR channel buffers. This is periodically done by ® sampling the DDRCOMP pin on the MCH. The Intel E7501 MCH calibrates using a 24.9 Ω ± 1% pull-down to ground. This may be implemented by routing a 15 mils wide trace to a...

  • Page 88: Dual Channel Ddrvref And Odtcomp

    ® ® ® Intel Pentium M Processor and Intel E7501 Chipset Platform Memory Interface Routing Guidelines Figure 47. Dual Channel DDRCOMP Resistive Compensation <1" DDRCOMP_x 24.9 Ω ± 1% NOTE: ‘x’ indicates channel A or B. 6.3.6.2.1 DDRCOMP Tuning It may be necessary to tune the DDR memory bus for optimum signal integrity based on your platform characteristics.

  • Page 89: Ddr Vref Voltage Divider

    The ODTCOMP reduces ringbacks and overshoots, and in some cases may help reduce the need for series termination. The Intel E7501 MCH has four DDRVREFs per channel (eight total). Route DDRVREF and ODTCOMP traces 5 mils wide. The ODTCOMP signal needs a 402 Ω pull-down resistor. (See Figure 50.).

  • Page 90: Dual Channel Ddrcvo

    ® ® ® Intel Pentium M Processor and Intel E7501 Chipset Platform Memory Interface Routing Guidelines 6.3.6.4 Dual Channel DDRCVO The MCH uses a compensation signal to adjust buffer characteristics and output voltage swing over temperature, process, and voltage skew. Calibration is done periodically by sampling the DDRCVO_x pins on the MCH.

  • Page 91: 2.5 Volt Decoupling Requirements

    ® ® ® Intel Pentium M Processor and Intel E7501 Chipset Platform Memory Interface Routing Guidelines Figure 52. DDR VTerm Plane Two Vias Per 1 Capacitor Ground Fill on to the Internal Ground Top Layer One 0.1 µF Decoupling Plane...

  • Page 92: 53 1-Dimm Per Channel Decoupling

    ® ® ® Intel Pentium M Processor and Intel E7501 Chipset Platform Memory Interface Routing Guidelines Figure 53. 1-DIMM Per Channel Decoupling 8 Tantulum 100 µF Capacitors Around The DIMMs DIMM DIMM 2 Vias Per Capacitor to 6 Ceramic 0.10 µF Caps...

  • Page 93: 54 2-Dimms Per Channel Decoupling

    ® ® ® Intel Pentium M Processor and Intel E7501 Chipset Platform Memory Interface Routing Guidelines Figure 54. 2-DIMMs Per Channel Decoupling 12 Tantulum 100 µF Capacitors Around The DIMMs DIMM DIMM DIMM DIMM 2 Vias Per Capacitor to 6 Ceramic 0.10 µF Caps...

  • Page 94: Single Channel Ddr Overview

    DIMMs should be populated furthest when a combination of single ranked and double ranked DIMMs are used. This recommendation is based on the signal integrity requirements of the DDR interface. Intel recommends checking for correct DIMM placement during BIOS initialization. Additionally, it is strongly recommended that all designs follow the DIMM ordering, SMBus...

  • Page 95: Single Channel 4-Dimm Implementation

    To determine if a registered DDR DIMM is a single-bank DIMM or a double-bank DIMM, refer to Distinguishing Between Single-Rank and Double-Rank Registered DDR DIMM Modules Application Note (AP-727) or contact your Intel representative for more information. Figure 57. Example of Proper Single Channel Rank Mixing...

  • Page 96: Unused Channel Termination

    ® ® ® Intel Pentium M Processor and Intel E7501 Chipset Platform Memory Interface Routing Guidelines Figure 58. Example of Incorrect Single Channel Rank Mixing 6.4.1 Unused Channel Termination Channel B is not used in a single channel configuration. Therefore, Channel B’s associated signals...

  • Page 97: Single Channel Source Synchronous Signal Group Routing

    ® ® ® Intel Pentium M Processor and Intel E7501 Chipset Platform Memory Interface Routing Guidelines 6.4.2 Single Channel Source Synchronous Signal Group Routing The MCH source synchronous signals are divided into groups consisting of data bits (DQ) and check bits (CB). An associated strobe (DQS) exists for each DQ and CB group, as shown in Table 42.

  • Page 98: Single Channel Source Synchronous Signal Group Routing Guidelines

    3. Route all data signals and their associated strobes on the same layer from MCH to Rtt. 4. The MCH to DIMM1 trace length is defined as Intel E7501 MCH die pad (PCB trace velocity equivalent, Section 12.6, “Length Tuning”) to DIMM1 pin.

  • Page 99: Single Channel Source Synchronous Topology Dimm Solution

    ® ® ® Intel Pentium M Processor and Intel E7501 Chipset Platform Memory Interface Routing Guidelines Figure 59. Single Channel Source Synchronous Topology DIMM Solution DDR VTERM (1.25V) DQ/CB Data Group Channel A Associated DQS Rs to DIMM to DIMM...

  • Page 100: Single Channel Command Clock Routing

    ® ® ® Intel Pentium M Processor and Intel E7501 Chipset Platform Memory Interface Routing Guidelines 6.4.3 Single Channel Command Clock Routing Only one differential clock pair is routed to each DIMM connector because the MCH only supports registered DDR DIMMs. All CMDCLK/CMDCLK# termination is on the DIMM modules. Route each clock and its compliment adjacent to each other.

  • Page 101: Single Channel Source Clocked Signal Group Routing

    ® ® ® Intel Pentium M Processor and Intel E7501 Chipset Platform Memory Interface Routing Guidelines 6.4.4 Single Channel Source Clocked Signal Group Routing The MCH drives the command clock signals and the source-clocked signals together. That is, the MCH drives the command clock in the center of the valid window, and the source-clocked signals propagate with the command clock signal.

  • Page 102: Single Channel Chip Select Routing

    ® ® ® Intel Pentium M Processor and Intel E7501 Chipset Platform Memory Interface Routing Guidelines 6.4.5 Single Channel Chip Select Routing The MCH provides eight chip select signals. Two chip selects must be routed to each DIMM (one for each side).

  • Page 103: Single Channel Clock Enable Routing

    ® ® ® Intel Pentium M Processor and Intel E7501 Chipset Platform Memory Interface Routing Guidelines 6.4.6 Single Channel Clock Enable Routing The MCH provides a single clock enable (CKE) signal. This signal is used during initialization to indicate that valid power and clocks are being applied to the DIMMs. Because the CKE signal has higher loading, it requires a lower impedance.

  • Page 104: Single Channel Dc Biasing Signals

    The MCH uses DDRCOMP_A to calibrate the DDR channel buffers. This is periodically done by ® sampling the DDRCOMP pin on the MCH. The Intel E7501 MCH calibrates using a 24.9 Ω ± 1% pull-down to ground. This may be implemented by routing a 15 mils wide trace to a...

  • Page 105: Single Channel Ddrvref And Odtcomp

    ® ® ® Intel Pentium M Processor and Intel E7501 Chipset Platform Memory Interface Routing Guidelines Table 49. DDRCOMP Routing Guidelines ® Parameter Intel E7501 MCH Topology pull-down Nominal Trace Width 15 mils Nominal Trace Spacing 20 mils Trace Length - MCH to Rtt <...

  • Page 106: Ddr Vref Voltage Regulator

    ® ® ® Intel Pentium M Processor and Intel E7501 Chipset Platform Memory Interface Routing Guidelines Figure 67. DDR VREF Voltage Regulator DDR VTT (1.25V) DDR VDD Voltage (2.5V) Regulator DDR VREF (1.25V) 10K ±1% Vout 0.1 µF 10K ±1% Figure 68.

  • Page 107: Single Channel Ddrcvo

    ® ® ® Intel Pentium M Processor and Intel E7501 Chipset Platform Memory Interface Routing Guidelines Figure 69. Routing Single Channel DDRVREF and ODTCOMP 402 Ω ± 1% ODTCOMP DDR Vref (1.25V) DDRVREF_A3 DDRVREF_A2 DDRVREF_A1 DDRVREF_A0 6.4.7.4 Single Channel DDRCVO The MCH uses a compensation signal to adjust buffer characteristics and output voltage swing over temperature, process, and voltage skew.

  • Page 108: Single Channel Ddr Signal Termination And Decoupling

    ® ® ® Intel Pentium M Processor and Intel E7501 Chipset Platform Memory Interface Routing Guidelines Figure 70. Single Channel DDRCVO Single Channel Routing Guidelines DDR VDD (2.5V) 49.9 Ω ± 1% < 1" DDRCVO_A 49.9 Ω ± 1% 1 nF 6.4.8...

  • Page 109: 2.5 V Decoupling Requirements

    ® ® ® Intel Pentium M Processor and Intel E7501 Chipset Platform Memory Interface Routing Guidelines Figure 71. DDR VTerm Plane Two Vias Per 1 Capacitor Ground Fill on to the Internal Ground Top Layer One 0.1 µF Decoupling Plane...

  • Page 110: Single Channel 2-Dimm Decoupling

    ® ® ® Intel Pentium M Processor and Intel E7501 Chipset Platform Memory Interface Routing Guidelines Figure 72. Single Channel 2-DIMM Decoupling 8 Tantulum 100 µF Capacitors Around The DIMMs DIMM DIMM 2 Vias Per Capacitor to 6 Ceramic 0.10 µF Caps...

  • Page 111: Single Channel 4-Dimm Decoupling

    ® ® ® Intel Pentium M Processor and Intel E7501 Chipset Platform Memory Interface Routing Guidelines Figure 73. Single Channel 4-DIMM Decoupling 12 Tantulum 100 µF Capacitors Around The DIMMs DIMM DIMM DIMM DIMM 2 Vias Per Capacitor to 6 Ceramic 0.10 µF Caps...
  • Page 112 ® ® ® Intel Pentium M Processor and Intel E7501 Chipset Platform Memory Interface Routing Guidelines Design Guide...

  • Page 113: Hub Interface

    ® ® ® Intel Pentium M Processor and Intel E7501 Chipset Platform Hub Interface Hub Interface Signal Naming Convention Figure 74 has the Hub Interface 2.0 and Hub Interface 1.5 signal naming convention for each component. This figure is intended to give a quick naming cross reference to designers. The specific guidelines and implementation on these signals are given in the following sections.

  • Page 114: Hub Interface 2.0 Implementation

    ® ® ® Intel Pentium M Processor and Intel E7501 Chipset Platform Hub Interface Hub Interface 2.0 Implementation ® The MCH and Intel P64H2 ballout assignments are optimized to simplify the Hub Interface routing between these devices. To allow for greater flexibility in design, a connector may be placed on the interface to access a Hub Interface 2.0 (HI2.0) agent that resides on an adapter card.
  • Page 115 35 mils of spacing from any adjacent signals to minimize effects that cause signal degradation. To break out of the MCH and Intel P64H2 package, the Hub Interface data signals may be routed 5/5 (1:1). The signals must separate to 5/15 (or strobes to 5/35) within 0.5 inch of the outer ball array.

  • Page 116: Hub Interface 2.0 Length Matching

    1. All signal lines with arrows depict the total length of the signal including the mother board trace length, MCH ® package trace length, and Intel P64H2 package trace length. 2. PUSTRBF and PUSTRBS length matching is the same as for PSTRBF and PSTRBS.

  • Page 117: Hub Interface 2.0 Generation/Distribution Of Reference Voltages

    The nominal Hub Interface 2.0 reference voltage is 0.350 V ± 5%. Each Hub Interface 2.0 on the ® MCH has a dedicated HIVREF pin to sample this reference voltage. Similarly, the Intel P64H2 has a dedicated reference voltage pin. In addition to the reference voltage, a reference swing...

  • Page 118: Hub Interface 2.0 Resistive Compensation

    The nominal Hub ® Interface 2.0 reference swing voltage should be 0.8 V ± 5% for the MCH and Intel P64H2. Each Hub Interface 2.0 on the MCH has a dedicated HISWNG pin to sample this reference swing voltage.

  • Page 119: Hub Interface 2.0 Decoupling Guidelines

    Hub Interface 2.0 Decoupling Guidelines ® To improve I/O power delivery, use two, 0.1 µF capacitors per component (i.e., MCH, Intel P64H2). These capacitors should be placed within 150-mils of each package, adjacent to the rows that contain the Hub Interface. When the layout allows, wide metal fingers running on the VSS side of the board should connect the VCC1_8 / VCC1_2 side of the capacitors to the VCC1_8 / VCC1_2 power pins.

  • Page 120: Hub Interface 1.5 Implementation

    ® ® ® Intel Pentium M Processor and Intel E7501 Chipset Platform Hub Interface Hub Interface 1.5 Implementation The Hub Interface 1.5 signals HI[7:0] are associated with HI_STBS and HI_STBF. For those familiar with Hub Interface 1.0, HI_STBF and HI_STBS are called HI_STB# and HI_STB, respectively.

  • Page 121: Hub Interface 1.5 Generation/Distribution Of Reference Voltages

    ® 0.7 V ± 5% for the Intel ICH3-S. This voltage is sampled by the MCH using HISWNG, and is sampled by the Intel ICH3-S using HITERM (see Table 58). Both HISWNG and HITERM may be generated locally with a single voltage divider circuit as shown in Figure Table 58.

  • Page 122: Hub Interface 1.5 Resistive Compensation

    ® ® Intel Pentium M Processor and Intel E7501 Chipset Platform Hub Interface The values of R1, R2, R3, R4 and R5 must be rated at ± 1% tolerance. The selected resistor values must also ensure that the reference voltage and reference swing voltage tolerance are maintained over the input leakage specification.

  • Page 123: Intel ® 82870P2 (Intel P64H2)

    82870P2 (Intel P64H2) is a peripheral chip that performs PCI/PCI-X bridging functions ® between the Hub Interface 2.0 and the PCI bus. The Intel P64H2 is an integral part of the Intel E7501 chipset, bridging the MCH and the PCI/PCI-X bus. On the primary bus, the Intel P64H2 uses a 16-bit data bus to interface with the Hub Interface 2.0, and on the secondary bus, it supports...

  • Page 124: General Pci-X Routing Guidelines

    Table 61 itemizes all timing critical and some of the non-critical signals. All of the topologies in the following sections itemize the lengths for the timing critical signals in configurations which Intel simulated. Table 61. Simulated Timing Critical Signals PxAD[63:0], PxC/BE[7:0]#, PxDEVSEL#, PxFRAME#, PxIRDY#, PxTRDY#, PxSTOP#, PxPERR#, PxSERR#,...

  • Page 125: Pci/Pci-X Routing Requirements (No Hot-Plug Switch)

    Table 63 documents the lengths for the configurations Intel simulated. These topologies may also be used for Hot-Plug Parallel mode configurations where a Hot-Plug switch is not used. Figure 83.

  • Page 126: Riser Card Topologies

    ® ® ® Intel Pentium M Processor and Intel E7501 Chipset Platform ® Intel 82870P2 (Intel P64H2) Figure 84. Typical Hot-Plug Topology Slot 1 P64H2 to Switch to Switch1 ® Intel Switch Slot P64H2 Slot 2 Switch to Switch to...

  • Page 127: Pci-X Riser Card Topology

    ® ® ® Intel Pentium M Processor and Intel E7501 Chipset Platform ® Intel 82870P2 (Intel P64H2) Figure 85 shows a PCI-X channel with a single connector used for a riser. When a one slot riser is used, the channel may be run up to PCI-X 133 MHz. When a three slot riser is used, the channel may be run up to PCI 66 MHz.

  • Page 128: Pci-X Two Devices Down-Routing Requirements

    ® ® ® Intel Pentium M Processor and Intel E7501 Chipset Platform ® Intel 82870P2 (Intel P64H2) Figure 87. Device Down After PCI-X Riser Card Topology Riser Dev ice ® Intel P64H2 to Riser Riser to Dev ice P64H2 Table 67.

  • Page 129: Clock Configuration

    ® ® ® Intel Pentium M Processor and Intel E7501 Chipset Platform ® Intel 82870P2 (Intel P64H2) Figure 89. Two Devices Down Card Topology Dev ice P64H2 to Dev ice ® Intel P64H2 Dev ice P64H2 to Dev ice Table 69.

  • Page 130: Loop Clock Configuration

    ® ® ® Intel Pentium M Processor and Intel E7501 Chipset Platform ® Intel 82870P2 (Intel P64H2) Figure 91. No Hot-Plug Clock Topology Slot or Device Down ® Intel Ω P64H2 Table 71. No Hot-Plug Clock Routing Length Parameters Clock Speed...

  • Page 131: Idsel Implementation

    PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0a, allows for other resistor values. See Figure 93 for an example of how to implement the ® coupling resistor. IDSEL mapping per Intel P64H2 pin is arbitrary. However, AD16 is reserved. Figure 93. IDSEL Sample Implementation Circuit ®...

  • Page 132: Hot-Plug Implementation

    ® ® ® Intel Pentium M Processor and Intel E7501 Chipset Platform ® Intel 82870P2 (Intel P64H2) Table 73. SMBus Address Configuration Value PAGNT[5] PAGNT[4] PBGNT[5] PBGNT[4] NOTE: There is no bit 0 because it is the read/write direction indicator.

  • Page 133: Hot-Removals

    ® ® ® Intel Pentium M Processor and Intel E7501 Chipset Platform ® Intel 82870P2 (Intel P64H2) 8.2.1.1 Hot-Removals 1. User selects a slot holding an enabled add-in card and requests that slot be disabled. a. User interacts with a software user interface to request that slot be disabled.

  • Page 134: Hot-Plug Switch Implementation

    NOTE: The pin names shown in the Intel P64H2 block are Hot-Plug slot signal names. For single-slot parallel mode, refer to Table 76 for the corresponding Intel P64H2 pin name. For dual-slot parallel mode, refer Table 78 for the corresponding Intel P64H2 pin name. Design Guide...

  • Page 135: Optional Attention Button

    The recommended method to support hot plug is to route the SCI interrupt output signal on the Intel P64H2 (pin PAIRQ7) to an available GPIO pin on the ICH3. A System Controlled Interrupt (SCI) is a system interrupt used by hardware to notify the operating system of ACPI events. SCI is an active-low, shareable, level-triggered interrupt.

  • Page 136: Hot-Plug Interrupt Routing Requirements

    ® ® ® Intel Pentium M Processor and Intel E7501 Chipset Platform ® Intel 82870P2 (Intel P64H2) 8.2.5 Hot-Plug Interrupt Routing Requirements The recommended method to support Hot-Plug is to route the SCI interrupt output signal on the ® Intel P64H2 (pin PAIRQ7) to an available GPIO pin on the ICH3.

  • Page 137: Pci Clock

    Table 76) to the Hot-Plug controller do not require ® any debouncing logic in this mode. This logic is contained within the Intel P64H2. The POWERON value for this input is determined by BIOS. However, it is recommended that BIOS define a logic 0 to represent that the slot may be powered on.

  • Page 138: Hot-Plug Multiplexed Signals In Single-Slot Parallel Mode

    Note that the placement of the signals should be such that the value driven by the Intel P64H2 in dual-slot parallel mode is the same value it would have driven when in serial mode. 3. In both parallel modes, the BUSEN# and CLKEN# signals become active low instead of active high as they are during serial mode.

  • Page 139: Smbus Address Considerations

    Note that the placement of the signals should be such that the value driven by the Intel P64H2 in dual-slot parallel mode is the same value it would have driven when in serial mode. 3. In both parallel modes, the BUSEN# and CLKEN# signals become active low instead of active high as they are during serial mode.

  • Page 140: Single-Slot Parallel Smbus Circuit

    3.3 V through an 8.2 kΩ ± 5% resistor to keep them from toggling. 8.2.7.10 Reference Schematic for Single-Slot Parallel Mode ® Note that the schematic in Figure 99 is based on definition and simulation of the Intel P64H2. The schematic has not been fully validated. Design Guide...

  • Page 141: Dual-Slot Parallel Mode

    ® ® ® Intel Pentium M Processor and Intel E7501 Chipset Platform ® Intel 82870P2 (Intel P64H2) Figure 99. Reference Schematic for Single-Slot Parallel Mode P xP C L K O [0 ] C L K P xP C L K O [6 ]...

  • Page 142: Debounced Hot-Plug Switch Input

    The switch inputs (PAIRQ[15] and PAIRQ[10] in this case—see Table 78) to the Hot-Plug ® controller do not require debouncing logic in this mode. This logic is contained within the Intel P64H2. 8.2.8.3 Comparator Circuit for PCIXCAP1/PCIXCAP2 Pins A comparator circuit is required for properly decoding the PCI/PCI-X capability of the slot. Refer to the PCI Local Bus Specification, Revision 2.2, for this circuit.
  • Page 143 LEDs are in the appropriate state (off), and the Q-switches remain disconnected. Note that the placement of the signals should be such that the value driven by the Intel P64H2 in dual slot parallel mode is the same value it would have driven when in serial mode.

  • Page 144: Smbus Address Considerations

    P64H2 is ready for it to become deasserted. Pull the PAGNT4 (BUSENB#) signals to 3.3 V through a 10 kΩ ± 5% resistor. The Intel P64H2 may be able to drive this signal to ground when the signal must be asserted.

  • Page 145: Three Or More Slot Serial Mode

    ® ® ® Intel Pentium M Processor and Intel E7501 Chipset Platform ® Intel 82870P2 (Intel P64H2) Figure 101. Reference Schematic for Dual-Slot Parallel Mode PxPCLKO [0] Note * All PCI signals muxed or not need to follow PCI spec 2.2 pullup requirements PxPCLKO [1] 3.3V...

  • Page 146: Required Additional Logic

    8.2.9.5 HPx_SLOT[2:0] The HPx_SLOT[2:0] pins are pull-ups/pull-downs that are used to determine the slot count and ® mode of operation for the Intel P64H2 Hot-Plug controller. These pins should be strapped to the proper slot count value. See Table 8.2.9.6...

  • Page 147: Pull-Ups/Pull-Downs In Three Or More Slot Serial Mode

    ® ® ® Intel Pentium M Processor and Intel E7501 Chipset Platform ® Intel 82870P2 (Intel P64H2) Table 79. Shift Register Input Data Byte 0 Byte 1 Byte 2 Byte 3 Slot 1 switch (0 = closed) Slot 1 fault# (0 = fault)

  • Page 148: Reference Schematic For Serial Mode

    8.2.10.1 PCIXCAP Pin Requirements During all modes of the Intel P64H2 Hot-Plug controller operation, the Intel P64H2 PCI/PCI-X interface pin PxPCIXCAP is not used. This pin should be tied to VCC3_3 through an 8.2 kΩ resistor to avoid having this line float.

  • Page 149: M66En Pin Requirements

    One possible solution to the issue described in the previous paragraphs is to place a single 5 kΩ ± 5% pull-up on the Intel P64H2 side of the isolation logic and a 5 kΩ ± 5% pull-up on the slot side after the isolation logic, but with its own isolation switch, which uses an inverted version of the bus enable control signal.

  • Page 150: M66En Isolation Switch Solution

    Intel P64H2 to drive the M66EN signals to ground. The Intel P64H2 PCI interface PxM66EN signal should be pulled to 3.3 V through a 100kΩ ± 5% resistor. This signal would then be connected to the individual slots through a reverse biased diode (one diode per slot).

  • Page 151: M66En Diode Solution

    ® ® ® Intel Pentium M Processor and Intel E7501 Chipset Platform ® Intel 82870P2 (Intel P64H2) Figure 105. M66EN Diode Solution 3.3V Slot Slot Slot Slot 100 kΩ PxM66EN 3.3V 3.3V 3.3V 3.3V Intel® 20 kΩ 20 kΩ 20 kΩ...
  • Page 152 ® ® ® Intel Pentium M Processor and Intel E7501 Chipset Platform ® Intel 82870P2 (Intel P64H2) Design Guide...

  • Page 153: O Controller Hub

    ICH3-S) IDE Interface ® This section contains guidelines for connecting and routing the Intel ICH3-S IDE interface. The ICH3-S has two independent IDE channels. This section provides guidelines for IDE connector cabling and motherboard design, including component and resistor placement, and signal termination for both IDE channels.

  • Page 154: Combination Host-Side/Device-Side Cable Detection

    IDE device. When a 40-conductor cable is detected, the system software must not enable modes faster than Ultra DMA Mode 2 (Ultra ATA/33). Intel recommends that cable detection be performed using a combination Host-Side/Device-Side detection mechanism. 9.1.2.1 Combination Host-Side/Device-Side Cable Detection Host-side detection (described in the ATA/ATAPI-4 Standard, Section 5.2.11) requires the use of...

  • Page 155: Ide Connector Requirements

    M Processor and Intel E7501 Chipset Platform ® I/O Controller Hub 3 (Intel ICH3-S) than 2. When ID Word 93, bit 13 is 1, an 80-conductor cable is present. When this bit is 0, a legacy slave (Device 1) is preventing proper cable detection and BIOS should configure the system as though a 40-conductor cable is present and notify the user of the problem.

  • Page 156: Spkr Pin Consideration

    Pentium M Processor and Intel E7501 Chipset Platform ® I/O Controller Hub 3 (Intel ICH3-S) SPKR Pin Consideration SPKR is used as both the output signal to the system speaker and as a functional strap. The strap function enables or disables the ‘TCO Timer Reboot function’ based on the state of the SPKR pin on the rising edge of PWROK.

  • Page 157: Usb

    ® ® Intel Pentium M Processor and Intel E7501 Chipset Platform ® I/O Controller Hub 3 (Intel ICH3-S) Figure 109. PCI Bus Layout Example ® Intel ICH3-S The ICH3-S contains three UHCI host controllers. Each UHCI controller includes a root hub with two separate USB ports, for a total of six USB ports.

  • Page 158: Usb Routing Parameters

    ® Intel Pentium M Processor and Intel E7501 Chipset Platform ® I/O Controller Hub 3 (Intel ICH3-S) 9.4.2 USB Routing Parameters Use the following separation guidelines. Recommended trace width and separation is 5-mils trace width with 6-mils spacing (90 Ω...

  • Page 159: Intel ® Ich3-S Smbus/Smlink Interface

    ASIC (e.g., Intel 82550) to access targets on the SMBus as well as the ICH3-S Slave interface. Additionally, the ICH3-S supports slave functionality, including the host Notify protocol, on the SMLink pins.

  • Page 160: Smbus Design Considerations

    Wire OR (optional) Controller Note: Intel does not support external access of the ICH3-S's Integrated LAN controller via the SMLink interface. In addition, Intel does not support access of the ICH3-S's SMBus Slave Interface by the ® ICH3-S's SMBus host controller. Refer to the Intel 82801CA I/O Controller Hub 3 (ICH3-S) Datasheet for full functionality descriptions of the SMLink and SMBus interface.

  • Page 161: Unified Vcc_Core Architecture

    Intel Pentium M Processor and Intel E7501 Chipset Platform ® I/O Controller Hub 3 (Intel ICH3-S) 9.5.2 Unified VCC_CORE Architecture Designing an SMBus using the ICH3-S is based on the power supply source for the SMBus microcontrollers. For the platform, all devices are powered by VCC3_3; therefore, the preferred design choice is the unified VCC3_3 architecture.

  • Page 162: Calculating The Physical Segment Pull-Up Resistor

    ® Intel Pentium M Processor and Intel E7501 Chipset Platform ® I/O Controller Hub 3 (Intel ICH3-S) Added Considerations for Mixed Architecture: • The bus switch must be powered by VCC_SUSPEND. • Devices that are powered by the VCC_SUSPEND well must not drive into other devices that are powered off.

  • Page 163: Real Time Clock (Rtc)

    Full-Swing 32.768kHz SUSCLK Output Signal ® For further information on the RTC, consult Intel application note AP-728 Intel ICH Family Real Time Clock (RTC) Accuracy and Considerations Under Test Conditions, available at: http://developer.intel.com/design/chipsets/applnots/292276.htm. This section presents the recommended hookup for the RTC circuit for the ICH3-S.

  • Page 164: Rtc External Circuit

    ® Intel Pentium M Processor and Intel E7501 Chipset Platform ® I/O Controller Hub 3 (Intel ICH3-S) 9.6.1 RTC External Circuit The ICH3-S RTC module requires an external oscillating source of 32.768 kHz connected on the RTCX1 and RTCX2 balls.

  • Page 165: External Capacitors

    Intel Pentium M Processor and Intel E7501 Chipset Platform ® I/O Controller Hub 3 (Intel ICH3-S) 9.6.3 External Capacitors To maintain the RTC accuracy, the external capacitor C3 must be 0.047 µF, and capacitor values C1 and C2 should be chosen to provide the manufacturer's specified load capacitance (Cload) for the crystal when combined with the parasitic capacitance of the trace, socket (when used), and package.

  • Page 166: Rtc Layout Considerations

    M Processor and Intel E7501 Chipset Platform ® I/O Controller Hub 3 (Intel ICH3-S) Note: The temperature dependency of crystal frequency is a parabolic relationship (ppm / degree squared). The effect of the changing crystal's frequency when operating at 0° C (25° C below room temperature) is the same when operating at 50°...

  • Page 167: Susclk

    RTC oscillation. Probing VBIAS requires the same technique as probing the RTCX1 and RTCX2 signals (using ® Op-Amp). See application note AP-728, Intel ICH Family Real Time Clock (RTC) Accuracy and Considerations Under Test Conditions, for further details on measuring techniques.

  • Page 168: Internal Lan Layout Guidelines

    Pentium M Processor and Intel E7501 Chipset Platform ® I/O Controller Hub 3 (Intel ICH3-S) Internal LAN Layout Guidelines The ICH3-S provides various options for integrated LAN capability. The platform supports several components depending on the target market. The guidelines use the term 82562ET to refer to both ®...

  • Page 169: Lci (Lan Connect Interface) Guidelines

    Intel Pentium M Processor and Intel E7501 Chipset Platform ® I/O Controller Hub 3 (Intel ICH3-S) 9.7.1 LCI (LAN Connect Interface) Guidelines This section contains guidelines on how to implement a Platform LAN Connect (PLC) device on a system motherboard using LCI. It should not be treated as a specification, and the system designer must ensure through simulations or other techniques that the system meets the specified timings.

  • Page 170: General Lan Routing Guidelines And Considerations

    ® ® ® Intel Pentium M Processor and Intel E7501 Chipset Platform ® I/O Controller Hub 3 (Intel ICH3-S) Table 84. LCI Routing Parameter Summary Parameter Requirements 60 Ω ± 15% due to signal integrity requirements. Trace Impedance (Z Trace Spacing Minimum of 100 mils from non-LCI signals.

  • Page 171: Trace Geometry And Length

    Pentium M Processor and Intel E7501 Chipset Platform ® I/O Controller Hub 3 (Intel ICH3-S) • For high-speed signals, the number of corners and vias should be kept to a minimum. When a 90 degree bend is required, it is recommended to use two 45-degree bends instead. Refer to Figure 120.

  • Page 172: Power And Ground Connections

    ® Intel Pentium M Processor and Intel E7501 Chipset Platform ® I/O Controller Hub 3 (Intel ICH3-S) • Physically group together all components associated with one clock trace to reduce trace length and radiation. • Isolate I/O signals from high speed signals to minimize crosstalk, which may increase EMI emission and susceptibility to EMI from other signals.

  • Page 173: Board Design

    Intel Pentium M Processor and Intel E7501 Chipset Platform ® I/O Controller Hub 3 (Intel ICH3-S) The following are guidelines that help reduce circuit inductance in both backplanes and motherboards: • Route traces over a continuous plane with no interruptions (don't route over a plane split).
  • Page 174 Pentium M Processor and Intel E7501 Chipset Platform ® I/O Controller Hub 3 (Intel ICH3-S) • Lack of symmetry between the two traces within a differential pair. (For each component and/ or via that one trace encounters, the other trace must encounter the same component or a via at the same distance from the PLC.) Asymmetry may create common-mode noise and distort the...

  • Page 175: Intel ® 82562Et/Intel ® 82562Em Guidelines

    M Processor and Intel E7501 Chipset Platform ® I/O Controller Hub 3 (Intel ICH3-S) should be exercised when a capacitor is put in either of these locations. When a capacitor is used, it should almost certainly be less than 22 pF (6 pF to 12 pF values have been used on past designs with reasonably good success).

  • Page 176: Intel ® 82562Et/Intel ® 82562Em Termination Resistors

    Platform LAN connect component (82562ET or 82562EM) as possible. This is due to the fact that these resistors are terminating the entire impedance that is seen at the termination source (i.e., Intel 82562ET), including the wire impedance reflected through the transformer. Figure 122 shows the Intel 82562ET/EM termination.

  • Page 177: Distance From Magnetics Module To Rj45 (Distance A)

    9.7.4.2 Distance from Intel® 82562ET to Magnetics Module (Distance B) Distance B should also be designed to be less than 1 inch between devices. The high-speed nature of the signals propagating through these traces requires that the distance between these components be closely observed.

  • Page 178: Termination Plane Capacitance

    Intel Pentium M Processor and Intel E7501 Chipset Platform ® I/O Controller Hub 3 (Intel ICH3-S) 9.7.5.1 Termination Plane Capacitance It is recommended that the termination plane capacitance equal a minimum value of 1500 pF. This helps reduce the amount of crosstalk on the differential pairs (TDP/TDN and RDP/RDN) from the unused pairs of the RJ45.

  • Page 179: Debug Port And Logic Analyzer Interface

    ® ® ® Intel Pentium M Processor and Intel E7501 Chipset Platform Debug Port and Logic Analyzer Interface Debug Port and Logic Analyzer Interface 10.1 ITP Support 10.1.1 Overview One key tool that is needed to debug BIOS, logic, signal integrity, general software, and general hardware issues involving CPUs, chipsets, SIOs, PCI devices, and other hardware in a platform design is the In Target Probe (ITP).

  • Page 180: Recommended Onboard Itp700Flex Implementation

    TDI, TMS and TRST# Routing Requirements Route the TDI signal between the ITP700FLEX connector and the Intel Pentium M processor. A 150 Ω ± 5% pull-up to VCCP (1.05 V) should be placed within ± 300 ps of the processor’s TDI pin.

  • Page 181: Tck And Tdo Routing Requirements

    ± 200 ps of the ITP700FLEX connector pin. Route the TDO signal from the Intel Pentium M processor to a 54.9 Ω ± 1% pull-up resistor to VCCP that should be placed close to the ITP700FLEX connector’s TDO pin. Then insert a 22.6 Ω...

  • Page 182: Reset# Routing Guidelines

    L3 + L4 – L5 = L2 (within ± 50 ps) There is no need for pull-up termination on the Intel Pentium M processor side of the RESET# net due to presence of AGTL+ on-die termination on the processor and the Intel E7501 MCH.
  • Page 183 Section 10.2.1, “ITP Signal Routing Guidelines”. 3. All of the needed terminations to ensure proper signal quality are integrated inside the Intel Pentium M processor AGTL+ buffers or inside the ITP700FLEX debug port. No need for any external components for the BPM[5:0]# signals.

  • Page 184: Intel ® Pentium ® M Processor Logic Analyzer Support

    CPUs, chipsets, SIOs, PCI devices, and other hardware in platform design is the Intel Pentium M processor system bus logic analyzer probe. This tool is widely used by various validation, test, and debug groups from third party BIOS vendors, OEMs, and other developers).

  • Page 185: Mechanical Considerations

    The LAI is installed between the processor socket and the Intel Pentium M processor. The LAI pins plug into the socket, while the Intel Pentium M processor plugs into a socket on the LAI. Cabling this part of the LAI egresses the system to allow an electrical connection between the Intel Pentium M processor and a logic analyzer.
  • Page 186 ® ® ® Intel Pentium M Processor and Intel E7501 Chipset Platform Debug Port and Logic Analyzer Interface Design Guide...

  • Page 187: Platform Power Delivery Guidelines

    E7501 chipset-based platform. There are many methods to implement a power delivery system, and this is only one example. A voltage regulator (VR) is used to regulate power to the core and Intel Pentium M processor ® system bus rails of the Intel Pentium M processor and the Intel E7501 chipset PSB.

  • Page 188: Processor Voltage Regulator Power Delivery Architectural Block Diagram

    V_3 is the output rail of the 3.3 volt VR. This is typically used to provide power to the VR Controller and miscellaneous logic and pull-ups. 11.2 Customer Reference Board Power Delivery ® ® ® Figure 127 shows the power delivery architecture for the Intel Pentium M processor and Intel E7501 chipset customer reference board. Design Guide...

  • Page 189: Power Delivery Example

    ® ® ® Intel Pentium M Processor and Intel E7501 Chipset Platform Platform Power Delivery Guidelines Figure 127. Power Delivery Example Intel® Voltage Vcc_core IMVP-IV Regulator Processor Vcc_core 0.7 - 1.708 V 32 A 0.7 - 1.708 V (Core) (Core) 32 A 2.5 V...

  • Page 190: Processor Core Voltage (Vcc_Core)

    M processor uses six voltage identification pins, VID[5:0], to support automatic selection of power supply voltages. The VID pins for the Intel Pentium M processor are CMOS outputs driven by the processor VID circuitry. For more details about VR design to support the Intel Pentium M processor power supply requirements .

  • Page 191: 191

    64 mA. This regulator is required in all designs. 11.2.9 1.8 VSB As stated before, the 1.8 VSB provides power to the resume logic within the Intel ICH3-S. This logic uses about 14 mA. This regulator is required in all designs. 11.2.10...

  • Page 192: Processor Power Delivery Design Guidelines

    11.3.2 Voltage Identification for Intel Pentium M Processor There are six voltage identification pins on the Intel Pentium M processor. These signals may be used to support automatic selection of V voltages. They are needed to cleanly support CC_CORE voltage specification variations on current and future processors. VID[5:0] is defined in Table 87 below.
  • Page 193 ® ® ® Intel Pentium M Processor and Intel E7501 Chipset Platform Platform Power Delivery Guidelines Table 87. VID vs. V Voltage CC_CORE CC_CORE CC_CORE 1.708 1.196 1.692 1.180 1.676 1.164 1.660 1.148 1.644 1.132 1.628 1.116 1.612 1.100 1.596 1.084...

  • Page 194: Vcc_Core

    CPU-PWRGD implemented by platform control logic. ® Figure 128 depicts a number of signals that may or may not be platform visible or used in an Intel ® ® Pentium M processor/Intel E7501 chipset design. For more details on the relationships and timing requirements between VR_ON, output supply stabilization, and all power good signals.

  • Page 195: Thermal Power Dissipation

    ® ® ® Intel Pentium M Processor and Intel E7501 Chipset Platform Platform Power Delivery Guidelines regulator may be programmed through an external resistor network. See Figure 129. VREF is used to set the highest output voltage in conjunction with the selection of R5 and R6 in the resistor network.

  • Page 196: Voltage Regulator Topology

    ® ® Intel Pentium M Processor and Intel E7501 Chipset Platform Platform Power Delivery Guidelines These technology improvements by themselves are not sufficient to effectively remove the heat generated during the high current demand and tighter voltage regulation required by today’s processors.

  • Page 197: Voltage Regulator Design Recommendations

    ® ® ® Intel Pentium M Processor and Intel E7501 Chipset Platform Platform Power Delivery Guidelines Figure 130. Voltage Regulator Multi-Phase Topology Example Voltage Regulator 11.3.7 Voltage Regulator Design Recommendations When laying out the processor power delivery circuit using a traditional Buck Voltage Regulator on...

  • Page 198: High Current Paths During Abrupt Load Current Changes

    ® ® ® Intel Pentium M Processor and Intel E7501 Chipset Platform Platform Power Delivery Guidelines Figure 132. High Current Path With Top MOSFET Turned ON Voltage Regulator Control Circuitry 11.3.7.2 High Current Paths During Abrupt Load Current Changes During abrupt changes in the load current, the bulk and decoupling capacitors must supply current for the brief period before the regulator circuit may respond.

  • Page 199: High Current Path With Bottom Mosfet(S) Turned On

    ® ® Intel Pentium M Processor and Intel E7501 Chipset Platform Platform Power Delivery Guidelines Dead Time there is a high current flow through the inductor, processor, ground, and the Schottky diode. The diode and its traces must be laid out in such as to minimize both stray inductance and resistance with short, fat traces or planes.
  • Page 200 ® ® ® Intel Pentium M Processor and Intel E7501 Chipset Platform Platform Power Delivery Guidelines • Bulk capacitors for V need three vias per pad when vias are not shared. Clusters of bulk and bypass capacitors may be clustered along the high current paths between the sense resistor and the processor.

  • Page 201: Processor Decoupling Recommendations

    11.3.8 Processor Decoupling Recommendations Intel recommends proper design and layout of the system board bulk and high frequency decoupling capacitor solution to meet the transient tolerance at the processor package balls. To meet the transient response of the processor, it is necessary to properly place bulk and high frequency capacitors close to the processor power and ground pins.

  • Page 202: Processor Side Bus Voltage Plane Decoupling

    10 x 0.1 µF 0.6 nH / 10 Place next to the Intel Pentium M processor CPU. ® † Place one capacitor close to the Intel Pentium M processor and one capacitor close to the Intel E7501 MCH. 11.3.8.5 GTLREF Layout and Routing Recommendations There is one AGTL+ reference voltage pin on the Intel Pentium M processor, GTLREF, which is used to set the reference voltage level for the AGTL+ signals (GTLREF).

  • Page 203: Mch Power Delivery Guidelines

    Figure 136 shows the recommended topology for generating GTLREF for the Intel Pentium M processor using a R1 = 1 k ± 1% and R2 = 2 k ± 1% resistive divider. Since the input buffer trip point is set by the 2/3* V on GTLREF and to allow tracking of V voltage fluctuations, no decoupling should be placed on the GTLREF pin.

  • Page 204: Ddr (2.5 V Power Plane)

    ® ® ® Intel Pentium M Processor and Intel E7501 Chipset Platform Platform Power Delivery Guidelines • thirteen 0.1 µF capacitors are recommended (with 900 pH to 1.1 nH inductance) and should be evenly spaced for the System Bus. At least seven of the capacitors must be within 0.5 inch of the outer row of balls to the MCH.

  • Page 205: Hub Interface (1.2 V Power Plane)

    ® ® ® Intel Pentium M Processor and Intel E7501 Chipset Platform Platform Power Delivery Guidelines 11.4.4 Hub Interface (1.2 V Power Plane) Seven, 0.1 µF capacitors should be used to improve I/O power delivery to the MCH. These capacitors should be placed within 150 mils of the MCH package, adjacent to the rows that contain the Hub Interface.

  • Page 206: Mch Power Sequencing Requirement

    ® ® ® Intel Pentium M Processor and Intel E7501 Chipset Platform Platform Power Delivery Guidelines Figure 139. Filter Topology for VCCAHI1_2 (Hub Interface) RLC Network Within 1" VCC_1.2 Within 1" of Ball 1 Ω 100 nH VCCAHI_1.2 100 µF 0.1 µF...

  • Page 207: Intel ® Ich3-S Power Delivery Guidelines

    1.8 V logic is powered up. Some signals that are defined as ‘Input-only’ actually have output buffers that are normally disabled, and the Intel ICH3-S may unexpectedly drive these signals when the 3.3 V supply is active while the 1.8 V supply is not.

  • Page 208: Example 1.8 V/3.3 V Power Sequencing Circuit

    Ω ± 1% When analyzing systems that may be ‘marginally compliant’ to the Two Volt Rule, attention must be paid to the behavior of the Intel ICH3-S’s RSMRST# and PWROK signals because they control internal isolation logic between the various power planes: •...

  • Page 209: V5Ref Sequencing

    0.7 V higher than V5REF. Also, V5REF must power down after VCC3_3, or before VCC3_3 within 0.7 V. The rule must be followed in order to ensure the safety of the Intel ICH3-S. When the rule is violated, internal diodes may attempt to draw power sufficient to damage the diodes from the VCC3_3 rail.

  • Page 210: Intel ® Ich3-S Power Rails

    Intel ICH3-S Decoupling Recommendations The Intel ICH3-S is capable of generating large current swings when switching between logic high and logic low. This condition could cause the component voltage rails to drop below specified limits. To avoid this, ensure that the appropriate amount of bulk capacitance is added in parallel to the voltage input pins.
  • Page 211 ICH3-S, Balls B23 and C23. Requires one 0.1 µF decoupling capacitor. V5REF_SUS is the reference voltage for some 5 V tolerant inputs in the Intel ICH3-S (USB data and over current signals). V5REF_SUS VCCSUS_3.3 must never exceed 0.7 V higher than V5REF_SUS.

  • Page 212: Intel ® P64H2 Power Requirements

    1.0 µF 100 µF (near regulator) 2.0 (VCC_1.8) † 0.1 µF 4.7 µF (near Intel P64H2) 3.3 V PCI/PCI-X (VCC_3.3) 1.0 µF 100 µF (near regulator) † In the case of the twenty 0.1 µF decoupling capacitors for the Vcc3.3V plane, it is recommended that at...

  • Page 213: Pcirst# Implementation

    P64H2 Power Sequencing Requirement The 1.8 V voltage must be valid before the first CLK66 pulse is driven to the Intel P64H2. This may be ensured by gating the CK408 clocks using a power good signal from the 1.8 V regulator. If the first CLK66 pulse is driven before 1.8 V is valid, the Intel P64H2 PLL may fail to correctly...
  • Page 214 ® ® ® Intel Pentium M Processor and Intel E7501 Chipset Platform Platform Power Delivery Guidelines Design Guide...

  • Page 215: High-Speed Design Concerns

    ® ® ® Intel Pentium M Processor and Intel E7501 Chipset Platform High-Speed Design Concerns High-Speed Design Concerns 12.1 Return Path The return path is the route current takes to return to its source. It may take a path through ground planes, power planes, other signals, or integrated circuits.

  • Page 216: Bulk Decoupling

    ® ® Intel Pentium M Processor and Intel E7501 Chipset Platform High-Speed Design Concerns The inductance of the system due to cables and power planes slows the power supply's ability to respond quickly to a current transient. Decoupling a power plane may be broken into several independent parts.

  • Page 217: Serpentine Routing

    ® ® ® Intel Pentium M Processor and Intel E7501 Chipset Platform High-Speed Design Concerns 12.3 Serpentine Routing A serpentine net is a transmission line that is routed in such a manner that sections of the net double back and couple to other segments of the same net (see Figure 148).

  • Page 218: Emi Design Considerations

    ® ® ® Intel Pentium M Processor and Intel E7501 Chipset Platform High-Speed Design Concerns 12.4 EMI Design Considerations As microprocessor amperage and speeds increase, the ability to contain the corresponding electromagnetic radiation becomes more difficult. Frequencies generated by these processors may be in the low gigahertz (GHz) range, which may impact both the system design and the electromagnetic interference (EMI) test methodology.

  • Page 219: Emi Design Considerations

    EMI Design Considerations The following sections describe design techniques that may be applied to minimize EMI emissions. Some techniques have been incorporated into Intel-enabled designs (differential clock drivers, selective clock gating, etc.), and some must be implemented by motherboard designers (trace routing, clocking schemes, etc.).

  • Page 220: Differential Clocking

    ® ® ® Intel Pentium M Processor and Intel E7501 Chipset Platform High-Speed Design Concerns Figure 151. Impact of Spread Spectrum Clocking on Radiated Emissions Δ non-SSC (1-δ)f 12.5.2 Differential Clocking Differential clocking requires that the clock generator supply both clock and clock-bar traces.

  • Page 221: Pci Bus Clock Control

    ® ® Intel Pentium M Processor and Intel E7501 Chipset Platform High-Speed Design Concerns Differential clocking may also reduce the amount of noise coupled to other traces, which improves signal quality and reduces EMI. I/O signals are particularly important because they often leave the system chassis (serial and parallel ports, keyboards, mouse, etc.), and radiate noise that has been...

  • Page 222: Length Tuning

    12.6 Length Tuning ® ® Note: This section does not apply to the Intel Pentium M processor system bus. High speed source synchronous interfaces have very small setup and hold windows. As a result, the signals as a group are very sensitive to skew. A common way to reduce skew is to tune all of the lengths such that the setup and hold windows have the same positional relationship.
  • Page 223 ® ® ® Intel Pentium M Processor and Intel E7501 Chipset Platform High-Speed Design Concerns Figure 154. Signal Length Solution Space with One Strobe minimum maximum Minimum_ Maximum_ signal signal Signal Signal flight time flight time Flight Time Flight Time...
  • Page 224 ® ® ® Intel Pentium M Processor and Intel E7501 Chipset Platform High-Speed Design Concerns Figure 156. Signal Length Solution Space with Maximum Tolerance Strobes Minimum_ Maximum_ Signal Signal Flight Time Flight Time Shorter_Strobe Flight Time Longer_Strobe Flight Time tolerance When the strobes have exactly the same flight time, then the signals have a solution space which is 2*tolerance wide.

  • Page 225: Flight Time Segment Analysis

    ® ® ® Intel Pentium M Processor and Intel E7501 Chipset Platform High-Speed Design Concerns 12.6.2 Flight Time Segment Analysis Length matching often requires package compensation. Every time a signal changes innerconnect or layer, there is an affect on flight time. The most effective way to calculate flight time is to break up each signal into segments of constant flight time, analyze those segments, and then add the segment together.

  • Page 226: Length Tuning Equation Derivation

    ® ® ® Intel Pentium M Processor and Intel E7501 Chipset Platform High-Speed Design Concerns 12.6.3 Length Tuning Equation Derivation When routing a motherboard, only one piece of the equation is a variable: PCB trace length . For example, when signals are tuned with respect to the strobe, the final equation used by a motherboard designer is derived as follows.
  • Page 227 Tolerance PCB_velocity ® The MCH package velocities and trace lengths are located in the Intel E7501 Chipset Memory Controller Hub (MCH) Datasheet , “Chipset Interface Trace Length Compensation” Chapter. The datasheet states that the trace delay due to signal velocity is the inverse of velocity. The MCH package trace delay due to signal velocity is 150 ps/in, so the velocity is (150 ps/in) .

  • Page 228: Bus Length Tuning Methodology

    Intel commonly provides a length tuning calculator spreadsheet. This calculator uses a “seed value.” This is the PCB length of an arbitrary signal, typically the signal with the shortest PCB length.

  • Page 229: Length Matching Equation

    ® ® ® Intel Pentium M Processor and Intel E7501 Chipset Platform High-Speed Design Concerns To compensate for package-induced skew, all source synchronous motherboard trace lengths are adjusted by the exact amount of Package Length Compensation (PLC). Equation 4 defines PLC for a particular signal.
  • Page 230 ® ® ® Intel Pentium M Processor and Intel E7501 Chipset Platform High-Speed Design Concerns Figure 161. Illustration of PLC Length Matching M CH P rocessor Shortest Signal Longest P ackage Longest P ackage P rocessor to M C H...

  • Page 231: System Bus Length Matching Example

    Intel E7501 Chipset Memory Controller Hub (MCH) Datasheet. Alternatively ® the processor and MCH package trace lengths may be found in the Intel Pentium M Processor System Bus Length Matching Spreadsheet. Contact your Intel representative for information about the Length Matching Spreadsheet tool.

  • Page 232: Intel ® Pentium ® M Processor Signal Package Lengths

    All the signals within the same group are routed to the same length ± 0.1-mil accuracy. The Intel Pentium M processor package traces are routed as micro-strip lines with a nominal characteristic impedance of 50 Ω ± 10%.

  • Page 233: Common Layout Pitfalls

    To minimize impedance for ground and power pins, like-signals should be tied together whenever possible. Figure 162 shows the proper method for grouping like-signals for the processor and ® Figure 163 shows the MCH grouping. The same methodology should be applied to the Intel ® P64H2 and Intel ICH3-S. Design Guide...
  • Page 234 ® ® ® Intel Pentium M Processor and Intel E7501 Chipset Platform High-Speed Design Concerns Figure 162. CPU Like-Signals Grouped CPU_Vcc Ground Vccp Figure 163. MCH Like-Signals Grouped 2.5V 1.2V 1.05V Ground Design Guide...

  • Page 235: Fill Areas Under Bgas

    To minimize impedance for ground and power pins, ensure power and ground fills are placed directly under the BGAs. Figure 164 shows the proper method for fills under the MCH. The ® ® same methodology should be applied to the processor, Intel P64H2 and Intel ICH3-S. Figure 164. MCH Fill 2.5V Fill 1.25V Fill 1.2V Fill...

  • Page 236: Signal Parallelism

    ® ® ® Intel Pentium M Processor and Intel E7501 Chipset Platform High-Speed Design Concerns 12.9.3 Signal Parallelism To minimize high-speed signal induced noise (cross-talk) limit or do not route signals on adjacent layers parallel to each. Figure 165 shows the proper and improper methods for routing signals on adjacent layers.

  • Page 237: Via Sharing

    ® ® ® Intel Pentium M Processor and Intel E7501 Chipset Platform High-Speed Design Concerns 12.9.4 Via Sharing To minimize impedance, traces should not share vias. Figure 166 shows the improper method of via sharing. Figure 167 shows how to correct via sharing.
  • Page 238 ® ® ® Intel Pentium M Processor and Intel E7501 Chipset Platform High-Speed Design Concerns Figure 167. Correct Via Sharing C808 and C726 corrected to have their own vias Design Guide...

  • Page 239: Necking Down

    ® ® ® Intel Pentium M Processor and Intel E7501 Chipset Platform High-Speed Design Concerns 12.9.5 Necking Down To maintain the current carrying capacity of a thicker power/ground trace do not neck the trace down. When a trace is necked down, the entire trace essentially takes on the current carrying capacity of the narrowest width thus decreasing the current capacity effect of the thicker traces.
  • Page 240 ® ® ® Intel Pentium M Processor and Intel E7501 Chipset Platform High-Speed Design Concerns Figure 169. Correct Necking Down Neck down corrected by adding additional trace. Traces are equal in length and width. Design Guide...

  • Page 241: Signals Crossing Plane Splits

    ® ® ® Intel Pentium M Processor and Intel E7501 Chipset Platform High-Speed Design Concerns 12.9.6 Signals Crossing Plane Splits Signals that cross an adjacent layers plane boundary is undesirable for two reasons: • The return current that runs in the reference plane wants to share its current with the adjacent layers reference plane it just crossed over.
  • Page 242 ® ® ® Intel Pentium M Processor and Intel E7501 Chipset Platform High-Speed Design Concerns Design Guide...

  • Page 243: Schematic Checklist

    ® ® ® Intel Pentium M Processor and Intel E7501 Chipset Platform Schematic Checklist Schematic Checklist 13.1 Processor Schematic Checklist Table 95. Processor Schematic Checklist (Sheet 1 of 5) Checklist Items Recommendations Comments ® ® Intel Pentium M Processor System Bus (PSB) Interface Signals...
  • Page 244 Refer to Section 5.1.7.1.4. Connect to the processor and the Intel ICH3-S. Connect to the Intel ICH3-S through a 0 Ω series STPCLK# resistor. Include 200 Ω ± 5% pull-up to VCCP. Connect to an Intel ICH-3 GPIO pin or customer...
  • Page 245 ® ® ® Intel Pentium M Processor and Intel E7501 Chipset Platform Schematic Checklist Table 95. Processor Schematic Checklist (Sheet 3 of 5) Checklist Items Recommendations Comments • When ITP700FLEX Is Not Used : • Pull up to VCCP with a 150 Ω resistor when –...
  • Page 246 10 µF ± 10% capacitors. • Place all caps near the Processor. Decouple with twelve 0.1 µF ± 10% capacitors VCCP • The Intel Pentium M processor and two 150 µF ± 10% capacitors contains 25 VCC pins. For testing purposes, pull-down to GND through a 54.9 Ω...
  • Page 247 For testing purposes, pull-down to VSSSENSE No Connect GND through a 54.9 Ω ± 1% resistor. ® Processor Signals Not Supported By the Intel E7501 Chipset • No Connect. • For testing purposes, a stuffing option should DPWR# be provided to pull-up to VCCP through a 1 K Ω...

  • Page 248: Mch Schematic Checklist

    HIT# HITM# HLOCK# HREQ[4:0]# HTRDY# RS[2:0]# XERR# ® ® Signals Not Supported by the Intel Pentium M Processor AP[1:0] BINIT# through a 1 K Ω ± 5% resistor. DP[3:0]# • Pull-up to V RSP# • See schematics for further details on stuffing HA[35:32]# options.
  • Page 249 Intel P64H2 and (For trace impedance = 50 Ω ± 10%). HIRCOMP_C MCH to adjust the buffer HIRCOMP_D • Tie the Intel P64H2’s RCOMP pin to characteristics to specific 61.9 Ω ± 1%, pull-up to 1.8 V. board characteristics. • Refer to Section 7.2.3.
  • Page 250 ® ® ® Intel Pentium M Processor and Intel E7501 Chipset Platform Schematic Checklist Table 96. MCH Schematic Checklist (Sheet 3 of 4) Checklist Items Recommendations Comments • This signal is used to calibrate the Host AGTL+ I/O buffer Tie each COMP pin to a 24.9 Ω ±1% pull-down...
  • Page 251 ® ® ® Intel Pentium M Processor and Intel E7501 Chipset Platform Schematic Checklist Table 96. MCH Schematic Checklist (Sheet 4 of 4) Checklist Items Recommendations Comments 1.2 V Seven 0.1 µF caps. Refer to Section 11.4.4. (Hub Interface) VCCA1_2 VCCAHI1_2 RLC filters.

  • Page 252: Intel ® Ich3-S Schematic Checklist

    Asserted by the Intel ICH3-S when Recommend 300 Ω ± 5% pull-up to CPU_VCC. CPUPWRGD all processor voltage supplies are Connect to the processor and the Intel ICH3-S. stable. FWH Interface Signals No extra pull-ups required. Connect straight to The Intel ICH3-S integrates FWH[3:0]/ LAD[3:0] 24 k Ω...
  • Page 253 • No pull-down resistors required. ICH3-S. • Refer to Section 9.1.3. • These signals have integrated • No extra series termination resistors. series resistors in the Intel PIORDY ICH3-S. SIORDY • 4.7 k Ω ± 5% pull-up to 3.3 V • Refer to Section 9.1.3.
  • Page 254 ® ® ® Intel Pentium M Processor and Intel E7501 Chipset Platform Schematic Checklist ® Table 97. Intel ICH3-S Schematic Checklist (Sheet 3 of 8) Checklist Items Recommendations Comments • The 10 k Ω resistor to GND prevents GPI from floating when no devices are present on either IDE interface.
  • Page 255 ® ® ® Intel Pentium M Processor and Intel E7501 Chipset Platform Schematic Checklist ® Table 97. Intel ICH3-S Schematic Checklist (Sheet 4 of 8) Checklist Items Recommendations Comments LAN Interface Signals Connect to LAN_CLK on Platform LAN Connect LAN_CLK Device.
  • Page 256 ® ® ® Intel Pentium M Processor and Intel E7501 Chipset Platform Schematic Checklist ® Table 97. Intel ICH3-S Schematic Checklist (Sheet 5 of 8) Checklist Items Recommendations Comments • These signals have integrated pull-ups of 24 k Ω .
  • Page 257 VCCSUS1.8 have reached their nominal voltages. • 10 k Ω ± 5% pull-down to ground. Disconnect from the Intel ICH3-S and leave not connected. Use 8.2 k Ω pull-up resistor to SUS_STAT# VCC_3.3 for remaining devices on LPC bus.
  • Page 258 ® ® ® Intel Pentium M Processor and Intel E7501 Chipset Platform Schematic Checklist ® Table 97. Intel ICH3-S Schematic Checklist (Sheet 7 of 8) Checklist Items Recommendations Comments RTC Signals • For noise immunity on VBIAS signal. VBIAS Use one 0.047 µF capacitor.
  • Page 259 ® ® ® Intel Pentium M Processor and Intel E7501 Chipset Platform Schematic Checklist ® Table 97. Intel ICH3-S Schematic Checklist (Sheet 8 of 8) Checklist Items Recommendations Comments USB Signals 18.2 Ω ± 1% pull-down to ground. USBRBIAS Integrated 15 k Ω pull-down, USBP[5:0]P No external resistors are required.

  • Page 260: Intel ® 82870P2 (Intel P64H2) Schematic Checklist

    • R4 = 261 Ω ± 1%, R5 = 332 Ω ± 1%, HI_VSWING R6 = 750 Ω ± 1%. • Decouple the Intel P64H2 pin with a 0.01 µF. • Decouple the network nodes with a 0.1 µF PCI/PCI-X Bus Interface Signals...
  • Page 261 8.2 k Ω ± 5% pull-up to 3.3 V. APICD[1:0] Hot Plug Interface Enabled PxPCIXCAP These PCI signals are connected ® to separate pins on the Intel P64H2. See Section 8.2.7.3, and 8.2 k Ω ± 5% pulled up to 3.3 V. Section 8.2.8.4...
  • Page 262 ® ® ® Intel Pentium M Processor and Intel E7501 Chipset Platform Schematic Checklist ® Table 98. Intel P64H2 Schematic Checklist (Sheet 3 of 5) Checklist Items Recommendations Comments A logic one on this pin indicates to the controller that the PCI slot should be immediately powered off.
  • Page 263 • Decoupling: VCC1.8 Refer to Section 11.6.2. – 2 X 1.0 µF capacitors near the Intel P64H2. – 1 X 100.0 µF capacitors near regulator. Connect to 3.3 V Power Supply. Decoupling: • 20 0.1 µF capacitors near the Intel P64H2.
  • Page 264 ® ® ® Intel Pentium M Processor and Intel E7501 Chipset Platform Schematic Checklist ® Table 98. Intel P64H2 Schematic Checklist (Sheet 5 of 5) Checklist Items Recommendations Comments 8.2 k Ω ± 5% pull-up to VCC3.3. TEST# 8.2 k Ω ± 5% pull-up to VCC3.3.

  • Page 265: Ck408 Schematic Checklist

    See schematic for reference circuit. 10 k Ω ± 5% pull-down to ground. FS[1] SCLK, SDTA Connect to the 3 V SMBus partition. Connect to the Intel ICH3-S using a 33 Ω ± 5% USB_48MHz Refer to Section 4.7. series resistor to ICH3_CLK48.
  • Page 266 ® ® ® Intel Pentium M Processor and Intel E7501 Chipset Platform Schematic Checklist Table 99. CK408 Schematic Checklist (Sheet 2 of 2) Checklist Items Recommendations Reason/Impact VSS, VSS_48MHz, Terminate to GND. Refer to Section 4.9. VSS_IREF 1 k Ω ± 5% pull-down to ground.

  • Page 267: Layout Checklist

    ® ® ® Intel Pentium M Processor and Intel E7501 Chipset Platform Layout Checklist Layout Checklist All trace width and spacing recommendations are derived from a target impedance and crosstalk sensitivity. This is based upon the stackup defined in Section 3.1.
  • Page 268 7.5 inches. RESET# RS[2:0]# TRDY# ICH3-S Interface Signals ® • Connect to the processor and the Intel ICH3-S. A20M# • Trace impedance = 50 Ω ± 10%. IGNNE# INIT# • Route traces using 5/10 mils (1:2) spacing.
  • Page 269 ® ® ® Intel Pentium M Processor and Intel E7501 Chipset Platform Layout Checklist Table 100. Processor Layout Checklist (Sheet 3 of 4) Checklist Items Recommendations Comments Processor In Target Probe (ITP) Signals When ITP700FLEX Is Used : Point to point connection to CPU pin.
  • Page 270 ® ® ® Intel Pentium M Processor and Intel E7501 Chipset Platform Layout Checklist Table 100. Processor Layout Checklist (Sheet 4 of 4) Checklist Items Recommendations Comments Processor Power and GND Signals • To satisfy damping requirements, total series resistance in the filter (from CPU_VCC to the top plate of the capacitor) must be at least 0.35 Ω...

  • Page 271: Intel ® E7501 Mch Layout Checklist

    ® ® ® Intel Pentium M Processor and Intel E7501 Chipset Platform Layout Checklist ® 14.2 Intel E7501 MCH Layout Checklist ® Table 101. Intel E7501 Chipset MCH Layout Checklist (Sheet 1 of 4) Checklist Items Recommendations Comments ® Intel E7501 Chipset MCH General Layout Recommendations •...
  • Page 272 ® ® ® Intel Pentium M Processor and Intel E7501 Chipset Platform Layout Checklist ® Table 101. Intel E7501 Chipset MCH Layout Checklist (Sheet 2 of 4) Checklist Items Recommendations Comments Host Interface Signals ADS# BNR# BPRI# BREQ0# CPURST# DBSY#...
  • Page 273 ® ® ® Intel Pentium M Processor and Intel E7501 Chipset Platform Layout Checklist ® Table 101. Intel E7501 Chipset MCH Layout Checklist (Sheet 3 of 4) Checklist Items Recommendations Comments • Route 40 Ω using a 7.5 mils wide trace.
  • Page 274 ® ® ® Intel Pentium M Processor and Intel E7501 Chipset Platform Layout Checklist ® Table 101. Intel E7501 Chipset MCH Layout Checklist (Sheet 4 of 4) Checklist Items Recommendations Comments Clocks and Reset Signals HCLKs should be length matched to the HCLKINP processor’s BCLK.

  • Page 275: Intel ® Ich3-S Layout Checklist

    ® ® ® Intel Pentium M Processor and Intel E7501 Chipset Platform Layout Checklist ® 14.3 Intel ICH3-S Layout Checklist ® Table 102. Intel ICH3-S Layout Checklist (Sheet 1 of 4) Checklist Items Recommendations Comments Processor Signals A20M# CPUSLP# FERR# IGNNE# See processor section of this checklist.
  • Page 276 (4.7 µF or greater OK) on each side of the that this is a robust design Intel 82562EM / Intel 82562ET component. recommendation. Place decoupling capacitors (0.1 µF) as close to the Intel 82562EM / Intel 82562ET component as possible. Design Guide...
  • Page 277 Comments Power Decoupling Use one 0.1 µF decoupling capacitor. V_CPU_IO[2:0] Locate within 100 mils of the Intel ICH3-S Used to pull-up all processor I/F signals. processor interface balls. Requires six 0.1 µF decoupling capacitors. Distribute around the Intel ICH3-S package...
  • Page 278 (such as USBP2P and USBP2N) should be no greater than 150 mils. • No termination resistors needed for USB. The Intel ICH3-S has internal 15 k Ω resistors. • 47 pF parallel capacitors may be placed as close to the USB connector as possible.

  • Page 279: Intel ® P64H2 Layout Checklist

    See MCH Hub Interface section of this checklist. PCI-X Interface Section 8.1 for complete list of topologies and lengths. ® • Group like signals together under the Intel • Refer to Section 12.9.1. P64H2 such as ground, 1.8 V, 3.3 V, etc. General Guidelines •...
  • Page 280 ® ® ® Intel Pentium M Processor and Intel E7501 Chipset Platform Layout Checklist Design Guide...
  • Page 281 Pentium M Processor and Intel E7501 Chipset Platform Schematics Schematics ® ® ® The following schematics for the Intel Pentium M processor/Intel E7501 chipset compatible platform Customer Reference Board (CRB) are included in this section. • System Block Diagram •...
  • Page 282 ® ® ® Intel Pentium M Processor and Intel E7501 Chipset Platform Schematics • Power Connector and Power OK Circuit • CPUVCC Regulator • CK-408B • FWH, LPC Connector (Debug) • SIO, Legacy I/O • 1.2 V Regulation • LAN Controller and Connector •...

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