Ssp Status Register (Sssr); Ssitr Bit Definitions - Intel PXA255 Developer's Manual

Setting any of these bits also causes the corresponding status bit(s) to be set in the SSP Status
Register (SSSR). The interrupt or service request caused by the setting of one of these bits remains
active until the bit is cleared.
This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.
Table 16-7. SSITR Bit Definitions
0x4140_000C
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
Reset ? ? ? ? ? ?
Bits Access
31:8
7 R/W
6 R/W
5 R/W
4:0
16.5.6

SSP Status Register (SSSR)

SSSR, shown in
receive FIFO service requests. Each of these hardware-detected events signals an interrupt request
to the interrupt controller. The status register also contains flags that indicate:
•
When the SSP is actively transmitting data
•
When the transmit FIFO is not full
•
When the receive FIFO is not empty
One interrupt signal is sent to the interrupt controller for each SSP. These events can cause an
interrupt:
•
Receiver time-out,
•
Receive FIFO overrun,
•
Receive FIFO request
•
Transmit FIFO request.
Intel® PXA255 Processor Developer's Manual
reserved
? ? ? ? ? ? ?
Name
— — reserved
TEST RECEIVE FIFO OVERRUN:
0 – No receive FIFO overrun service request is generated.
TROR
1 – Generates a non-maskable Interrupt to the CPU. No DMA request
TEST RECEIVE FIFO SERVICE REQUEST:
0 – No receive FIFO service request is generated.
TRFS
1 – Generates a non-maskable Interrupt to the CPU and a DMA
TEST TRANSMIT FIFO SERVICE REQUEST:
0 – No transmit FIFO service request is generated.
TTFS
1 – Generates a non-maskable Interrupt to the CPU and a DMA
— — reserved
Table 16-8 contains bit fields that signal overrun errors and the transmit and
SSITR
? ? ? ? ? ? ? ?
is generated.
request for the receive FIFO.
request for the transmit FIFO.
Network SSP Serial Port
Network SSP Serial Port
8 7 6 5 4 3
reserved
? ? ? 0 0 0 ? ?
Description
2 1 0
? ? ?
16-25