Bit Byte Address Bits Ma[1:0] For Reads Based On Dqm[3:0]; Bit Byte Address Bit Ma[0] For Reads Based On Dqm[1:0]; Sa-1111 Register Bit Definitions - Intel PXA255 Developer's Manual

Table 6-21. 32-Bit Byte Address Bits MA[1:0] for Reads Based on DQM[3:0]
Anything Else
Table 6-22. 16-Bit Byte Address Bit MA[0] for Reads Based on DQM[1:0]
Table 6-23. SA-1111 Register Bit Definitions
0X4800 0064
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
Reset ? ? ? ? ? ?
Bits Access
31:6
5
4
3
2
1
0
Intel® PXA255 Processor Developer's Manual
DQM[3:0]
0000
0001
1101
1001
0101
1011
0011
0111
DQM[1:0]
00
10
01
11
? ? ? ? ? ? ?
Name
— Reserved Writes must set this field to zero and Read values should be ignored
R/W SA1111_5 Enables SA-1111 Compatibility Mode for Static Memory Partition 5.
R/W SA1111_4 Enables SA-1111 Compatibility Mode for Static Memory Partition 4.
R/W SA1111_3 Enables SA-1111 Compatibility Mode for Static Memory Partition 3.
R/W SA1111_2 Enables SA-1111 Compatibility Mode for Static Memory Partition 2.
R/W SA1111_1 Enables SA-1111 Compatibility Mode for Static Memory Partition 1.
R/W SA1111_0 Enables SA-1111 Compatibility Mode for Static Memory Partition 0.
MA[1:0]
00
01
10
11
00
MA[0]
0
0
1
0
SA1111
? ? ? ? ? ? ? ?
Description
Memory Controller
8 7 6 5 4 3
? ? ? ? ? 0 0 0
2 1 0
0 0 0
6-45