Flash Memory Interface (Asynchronous/Synchronous); Flash Memory Signals; Flash Interface Signals - Intel PXA27 Series Design Manual

6.5.2

Flash Memory Interface (Asynchronous/Synchronous)

Memory types are programmable through the memory interface configuration registers. Refer to
®
the Intel
configuration registers.
Six chip selects control the static memory interface, nCS<5:0>. All the chip selects are
configurable for non-burst ROM or flash memory, burst ROM or flash, SRAM, or SRAM-like
variable latency I/O devices. The variable latency I/O interface differs from SRAM in regard to its
ability to allow the data ready input signal (RDY) to insert a variable number of memory-cycle-
wait states. Program the data bus width for each chip select region to 16-bit (D<15:0>) or 32-bit
(D<31:0>). nCS<3:0> signals are also configurable for synchronous static memory.
MA2 connects to the LSB of the static memory when the memory devices used are connected as
32-bit wide data bus interface. MA1 connects to the LSB of the static memory when the memory
devices used are connected as 16-bit wide data bus interface.
6.5.2.1

Flash Memory Signals

See Table 6-9
Table 6-9. Flash Interface Signals
Signal Name
nCS<5:0>
MA<25:0>
nWE
nOE
MD<31:0>
SDCLK0
nSDCAS
RDnWR
BOOT_SEL0
®
Intel PXA27x Processor Design Guide
PXA27x Processor Family Developers Manual for detail information on the
for the list of signals required to interface to flash memory devices.
Direction Polarity
Output Active Low
Output NA
Output Active Low
Output Active Low
Bidirectional NA
Additional I/O Signals Required to support Synchronous Flash Memory
Output Active High
Output Active Low
Output Active High
Tied at board
Input
level

Flash Interface Signals

Chip selects for static memory
Only nCS<3:0> is configurable for synchronous flash
memory
Output address to all memory types
NOTE: Do not use MA0 for byte addressing because all
flash devices must have a minimum bus width of 16
bits when interfacing to the PXA27x processor
memory controller. Use MA0 to address the upper
64 MBytes of memory within a 128 MBytes partition.
Write enable for SDRAM and static memory
Output enable for static memory
Bidirectional data for all memory types
SDCLK<0> is for synchronous flash memory
nADV (address strobe) for synchronous flash
Miscellaneous I/O Signals
Data direction signal to be used by output transceivers
0 = MD<31:0> is driven by the PXA27x processor
1 = MD<31:0> is not driven by the PXA27x processor
Boot Select signals allows two possible configuration for
booting – indicates the type of boot memory possessed by
the system
0 = 32-bit ROM/flash
1 = 16-bit ROM/flash
System Memory Interface
Description
II:6-15