Intel PXA255 Developer's Manual page 60

System Architecture
Table 2-8. System Architecture Register Address Summary (Sheet 10 of 12)
Unit Address
0x40F0_002C
0x40F0_0030
SSP 0x4100_0000
0x4100_0000
0x4100_0004
0x4100_0008
0x4100_000C
0x4100_0010
MMC
0x4110_0000
Controller
0x4110_0000
0x4110_0004
0x4110_0008
0x4110_000C
0x4110_0010
0x4110_0014
0x4110_0018
0x4110_001C
0x4110_0020
0x4110_0024
0x4110_0028
0x4110_002C
0x4110_0030
0x4110_0034
0x4110_0038
0x4110_003C
0x4110_0040
0x4110_0044
Clocks
0x4130_0000
Manager
0x4130_0000
0x4130_0004
0x4130_0008
Network SSP 0x4140_0000
0x4140_0000
0x4140_0004
0x4140_0008
0x4140_000C
0x4140_0010
0x4140_0028
2-30
Register Symbol
— Reserved
RCSR Reset Controller Status Register
SSCR0 SSP Control Register 0
SSCR1 SSP Control Register 1
SSSR SSP Status Register
SSITR SSP Interrupt Test Register
SSDR (Write / Read) SSP Data Write Register/SSP Data Read Register
MMC_STRPCL Control to start and stop MMC clock
MMC_STAT MMC Status Register (read only)
MMC_CLKRT MMC clock rate
MMC_SPI SPI mode control bits
MMC_CMDAT Command/response/data sequence control
MMC_RESTO Expected response time out
MMC_RDTO Expected data read time out
MMC_BLKLEN Block length of data transaction
MMC_NOB Number of blocks, for block mode
MMC_PRTBUF Partial MMC TXFIFO FIFO written
MMC_I_MASK Interrupt Mask
MMC_I_REG Interrupt Register (read only)
MMC_CMD Index of current command
MMC_ARGH MSW part of the current command argument
MMC_ARGL LSW part of the current command argument
MMC_RES Response FIFO (read only)
MMC_RXFIFO Receive FIFO (read only)
MMC_TXFIFO Transmit FIFO (write only)
CCCR Core Clock Configuration Register
CKEN Clock Enable Register
OSCC Oscillator Configuration Register
NSSCR0 NSSP Control Register 0
NSSCR1 NSSP Control Register 1
NSSSR NSSP Status Register
NSSITR NSSP Interrupt Test Register
NSSDR NSSP Data Read/Write Register
NSSTO NSSP Time Out Register
Register Description
Intel® PXA255 Processor Developer's Manual