Gfer0 Bit Definitions; Gfer1 Bit Definitions; Gfer2 Bit Definitions - Intel PXA255 Developer's Manual

System Integration Unit
Table 4-18. GFER0 Bit Definitions
Physical Address
0x40E0_003C
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
Reset 0 0 0 0 0 0
Bits Name
<31:0> FE[x]
Table 4-19. GFER1 Bit Definitions
Physical Address
0x40E0_0040
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
Reset 0 0 0 0 0 0
Bits Name
<31:0> FE[x]
Table 4-20. GFER2 Bit Definitions
Physical Address
0x40E0_0044
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
reserved
Reset 0 0 0 0 0 0
Bits Name
<31:21>
<20:0> FE[x]
4-14
0 0 0 0 0 0 0
GPIO Pin 'x' Falling Edge Detect Enable (where x = 0 through 31).
0 – Disable falling-edge detect enable.
1 – Set corresponding GEDR status bit when a falling edge is detected on the GPIO pin
0 0 0 0 0 0 0
GPIO Pin 'x' Falling Edge Detect Enable (where x = 32 through 63).
0 – Disable falling-edge detect enable.
1 – Set corresponding GEDR status bit when a falling edge is detected on the GPIO pin
0 0 0 0 0 0 0
— reserved
GPIO Pin 'x' Falling Edge Detect Enable (where x = 64 through 84).
0 – Disable falling-edge detect enable.
1 – Set corresponding GEDR status bit when a falling edge is detected on the GPIO pin
GFER0
0 0 0 0 0 0 0 0
Description
GFER1
0 0 0 0 0 0 0 0
Description
GFER2
0 0 0 0 0 0 0 0
Description
Intel® PXA255 Processor Developer's Manual
System Integration Unit
8 7 6 5 4 3
0 0 0 0 0 0 0 0
System Integration Unit
8 7 6 5 4 3
0 0 0 0 0 0 0 0
System Integration Unit
8 7 6 5 4 3
0 0 0 0 0 0 0 0
2 1 0
0 0 0
2 1 0
0 0 0
2 1 0
0 0 0