Rom Interface; Asynchronous Static Memory And Variable Latency I/O Capabilities - Intel PXA255 Developer's Manual

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Memory Controller

Table 6-25. Asynchronous Static Memory and Variable Latency I/O Capabilities

burst writes)

ROM Interface

The processor provides programmable timing for both burst and non-burst ROMs. The RDF field

in MSCx is the latency (in memory clock cycles) for the first, and all subsequent, data beats from

non-burst ROMs, and the first data beat from a burst ROM. RDN is the latency for the burst data

beats after the first for burst ROMs. RRR delays the following access to a different memory space

to allow time for the current ROM to three-state the data bus.

RRR must be programmed with the maximum t

For hardware reset initialization values, refer to

address space corresponding to nCS0 is accessed. The processor supports a ROM burst size of 1, 4,

or 8 by configuring the MSCx[RTx] register bits to 0, 2 or 3 respectfully.

provides a comparison of supported Asynchronous Static Memory types.

Timing (Memory Clocks)

value, as specified by the ROM manufacturer.

6.8. MSC0[15:0] is selected when the

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