Ssp Controller Register Summary - Intel PXA255 Developer's Manual

8.7.4.8 Receive FIFO Level (RFL)
This bit indicates the one less than number of entries in the Receive FIFO.
This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.
8.8

SSP Controller Register Summary

Table 8-7
Table 8-7. SSP Controller Register Summary
0x4100_0000
0x4100_0004
0x4100_0008
0x4100_000C
0x4100_0010
Intel® PXA255 Processor Developer's Manual
shows the SSP registers associated with the SSP controller and their physical addresses.
Address Abbreviation
SSCR0
SSCR1
SSSR
SSDR (Write / Read)
Synchronous Serial Port Controller
SSP Control Register 0
SSP Control Register 1
SSP Status Register
— reserved
SSP Data Write Register/SSP Data Read Register
Full Name
8-19