Interfacing With 8-, 16-, And 32-Bit Memories - Intel Embedded Intel486 Hardware Reference Manual

Table 4-4. Data Pins Read with Different Bus Sizes
BE3# BE2#
1 1
1 1
1 0
0 0
1 1
1 0
0 0
1 0
0 0
0 1
Valid data is only driven onto data bus pins corresponding to asserted byte enables during write
cycles. Other pins in the data bus are driven but they contain no valid data. Unlike the Intel386
processor, the Intel486 processor does not duplicate write data onto parts of the data bus for
which the corresponding byte enable is deasserted.
4.1.3

Interfacing with 8-, 16-, and 32-Bit Memories

In 32-bit physical memories, such as the one shown in
byte address that is a multiple of four. A31–A2 are used as a 4-byte word select. BE3#–BE0# se-
lect individual bytes within the 4-byte word. BS8# and BS16# are deasserted for all bus cycles
involving the 32-bit array.
For 16- and 8-bit memories, byte swapping logic is required for routing data to the appropriate
data lines and logic is required for generating BHE#, BLE# and A1. In systems where mixed
memory widths are used, extra address decoding logic is necessary to assert BS16# or BS8#.
Intel486™
Processor
"HIGH"
Figure 4-3. Intel486™ Processor with 32-Bit Memory
BE1# BE0#
1 0
0 0
0 0
0 0
0 1
0 1
0 1
1 1
1 1
1 1
32
Data Bus (D31–D0)
Address Bus
(BE3#–BE0#, A31–A2)
BS8#
BS16#
"HIGH"
w/o BS8#/BS16#
D7–D0
D15–D0
D23–D0
D31–D0
D15–D8
D23–D8
D31–D8
D23–D16
D31–D16
D31–D24
Figure 4-3, each 4-byte word begins at a
32-Bit
Memory
BUS OPERATION
w BS8# w BS16#
D7–D0 D7–D0
D7–D0 D15–D0
D7–D0 D15–D0
D7–D0 D15–D0
D15–D8 D15–D8
D15–D8 D15–D8
D15–D8 D15–D8
D23–D16 D23–D16
D23–D16 D31–D16
D31–D24 D31–D24
4-5