Figure 46: Power-On Sequence Timing Diagram; Figure 47. Power-Off Sequence Timing Diagram - Intel Pentium 4 Design Manual

R

Figure 46: Power-on Sequence Timing Diagram

VID_GOOD
VCC_CPU
PWRGOOD
RESET#

Figure 47. Power-off Sequence Timing Diagram

® ®
Intel Pentium 4 Processor / Intel
Power Up Sequence
VCCVID
Ta
VID[4:0]
BCLK
Ta= 1ms minimum (VCCVID > 1V to VID_GOOD high)
Tb= 50ms maximum (VID_GOOD to Vcc valid maximum time)
Tc= T37 (PWRGOOD inactive pulse width) = 10 BCLKs min
Td= T36 (PWRGOOD to RESET# de-assertion time) = 1ms(min), 10ms(max)
Note: VID_GOOD is not a processor signal. This signal is routed to the
output enable pin of the voltage regluator control silicon.
Power Down Sequence
VCC_CPU
PWRGOOD
VCCVID
VID_GOOD
VID[4:0]
Note: VID_GOOD is not a processor signal. This signal is routed to the
output enable pin of the voltage regluator control silicon.
1. This timing diagram is not intended to show specific times. Instead a
general ordering of events with respect to time should be observed.
2. When VCCVID is less than 1V, VID_GOOD must be low.
3. Vcc must be disabled before VID[4:0] becomes invalid.
®
850 Chipset Family Platform Design Guide
Tb
Tc
System Bus Routing
Td
Power-on_Sequence_Timing
Power-off_Sequence_Timing
81