Serial Audio Interrupt Mask Register (Saimr); Serial Audio Data Register (Sadr); Saimr Bit Descriptions; Sadr Bit Descriptions - Intel PXA255 Developer's Manual

Inter-Integrated-Circuit Sound (I2S) Controller
14.6.6

Serial Audio Interrupt Mask Register (SAIMR)

Writing a one to the corresponding bit position in the SAIMR, shown in
corresponding interrupt signal.
This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.
Table 14-10. SAIMR Bit Descriptions
Physical Address
0x4040_0014
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
Reset 0 0 0 0 0 0
Bits Name
31:7
6 ROR
5
4
3
2:0
14.6.7

Serial Audio Data Register (SADR)

Writing a 32-bit sample to SADR, shown in
Reading this register flushes a 32-bit sample from the Receive FIFO.
Figure 14-3
This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.
Table 14-11. SADR Bit Descriptions
Physical Address
0x4040_0080
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
Reset 0 0 0 0 0 0
Bits Name
31:16
15:0
14-14
Serial Audio Interrupt Mask Register
reserved
0 0 0 0 0 0 0
— reserved
Enable Receive FIFO Overrun condition based interrupt.
TUR Enable FIFO Under-run condition based interrupt.
RFS Enable Receive FIFO Service Request based interrupt.
TFS Enable Transmit FIFO Service Request based interrupt.
— reserved
illustrates data flow through the FIFOs and SADR.
Serial Audio Data Register
DTH
0 0 0 0 0 0 0
DTH Right data sample
DTL Left data sample
0 0 0 0 0 0 0 0
Description
Table 14-11, updates the data into the Transmit FIFO.
0 0 0 0 0 0 0 0
Description
Intel® PXA255 Processor Developer's Manual
Table 14-10, enables the
2
I S Controller
8 7 6 5 4 3
0 0 0 0 0 0 0 0
2
I S Controller
8 7 6 5 4 3
DTL
0 0 0 0 0 0 0 0
2 1 0
reserved
0 0 0
2 1 0
0 0 0